44 nd DAC, June 4-8, 2007 Processor External Interrupt Verification Tool (PEVT) Fu-Ching Yang, Wen-Kai Huang and Ing-Jer Huang Dept. of Computer Science and Engineering National Sun Yat-Sen University, Kaohsiung Taiwan

2/22 Motivation Microprocessor verification Microprocessor verification –Instruction-based verification – Branch prediction, Data hazard, etc… –External interrupt verification Why the external interrupt verification requires automation Why the external interrupt verification requires automation –External interrupt is an unexpected event –Tightly related to instruction –Trigger timing must be precise –Pipelined behavior must keep precise Processor Add instruction Sub instructionJPEGMPEG FIQ IRQ Abort ? Fetch Decode Execute1 Execute2 Execute3 INT. vectorSRV. RTN. addr. Fetch Hold Decode ExecuteFetch Decode Execute IRQ FIQ Dabort Pabort FIQ IRQ

3/22 Comparison with manual approach Processor External Interrupt Verification Tool (PEVT) Processor External Interrupt Verification Tool (PEVT) – –Automatically insert external interrupt signals – –Automatically insert instructions – –Automatically verify the microprocessor – – RTL level – – Cycle accurate –Time-efficiency –High functional coverage

4/22 Proposed Verification Framework Required micro-architecture information Required micro-architecture information –Microprocessor pipeline stages –Instruction cycles –External interrupt information – Instruction’s relationship with external interrupt Fetch Decode Execution Load 3-cycle instruction Execution2 Execution3 3 cycles IRQ INT. Vector Execution1

5/22 Proposed Verification Framework Exception Description Language (EXPDL) Exception Description Language (EXPDL) –Microprocessor model Assertion rule database Assertion rule database –Processor-independent verification rules –Extendable – Individual interrupt – Concurrent interrupt – Nested interrupt PEVT generates verification cases PEVT generates verification cases –Combine EXPDL and assertion rule database For automatic RTL verification For automatic RTL verification –Generate trigger – Comprise HW and SW –Generate monitor hardware Automatic External Interrupt HW/SW Generation

6/22 Exception Description Languages (EXPDL) Architecture Description Language Architecture Description Language LISP-like language LISP-like language Based on EXPRESSION Based on EXPRESSION –Cycle-accurate simulation –Instruction set information -> Instruction cycles –Structure information -> pipeline stages –Can’t describe interrupt behaviors – Extensions – Exception Description –Instruction’s relationship with external interrupt –Vector address –Trigger time : legal interrupt arrival time –Action time : when the microprocessor responses –Etc … Automatic External Interrupt HW/SW Generation

7/22 Assertion rule data base Automatic External Interrupt HW/SW Generation

8/22 Individual Interrupts For (each interrupt source i) for( each instruction j in processor’s instruction-set) { for( every cycle k of the instruction j) generate a test case to trigger interrupt i at k cycle of instruction j } IRQ Pabort Dabort FIQ Fetch Decode Execute1 Execute2 Execute3 Mem. access Load Only one external interrupt arrives before the microprocessor accepts another one Only one external interrupt arrives before the microprocessor accepts another one 8 individual interrupt for load instruction

9/22 Concurrent interrupts For (each instruction j in processor’s instruction set) { Find out the legal time slot of instruction j for all external interrupt Select 2..n external interrupts to trigger For( each combination) generate a test case to trigger interrupt i and i+1 and...n while executing instruction j } Multiple external interrupts arrive before the microprocessor responses to any of them Multiple external interrupts arrive before the microprocessor responses to any of them IRQ Pabort Dabort FIQ Fetch Decode Execute1 Execute2 Execute3 Mem. access Load IRQ Pabort Dabort FIQ

10/22 Graph Model for Nested Interrupts ARM7 One nested interrupt case The microprocessor can accept another external interrupt when executing the interrupt service routine caused by a previous interrupt –State : microprocessor’s mode –Directed edge : legal mode transition from predecessor state to successor state –Path : A legal nested interrupt mode transition Depth-First-Search to find all cases Depth-First-Search to find all cases PIC16

11/22 Verification environment Automatic External Interrupt HW/SW Generation

12/22 Verify Wait Verify Automatic verification mechanism Software trigger IRQ INT. Vector SRV. RTN. addr. Fetch Decode Load Exe.3 Exe.1 Exe.2 n cycles Instruction address Match T= A= 2 Trigger IRQ

13/22 Summary of Generated Test Cases Interrupt behavior # of test cases Simulation time (cycles)(sec.) Individual interrupt , Concurrent interrupt , Nested interrupt 1057,98038 Total432988, Microprocessor under verify : ARM7 Microprocessor under verify : ARM7 SUN Blade 2000 workstation SUN Blade 2000 workstation Every case takes 20 cycles on average to complete Every case takes 20 cycles on average to complete More cases can be verified More cases can be verified –Automatically

14/22 Verification hardware Simple hardware Simple hardware Good for FPGA and chip Good for FPGA and chip Verification module Code size Interrupt Activator 129 lines Monitor Engine 127 lines V-ROM 27 k-bytes

15/22 Bugs found Branch instruction ignores interrupt Branch instruction ignores interrupt –Individual interrupt The return address of an interrupted 2-cycle MOV instruction is wrong The return address of an interrupted 2-cycle MOV instruction is wrong –Individual interrupt Latency in external interrupt Latency in external interrupt –Individual interrupt

16/22 Conclusion An architecture description language extension is proposed An architecture description language extension is proposed A CAD tool is proposed to verify the interrupt behavior of processors A CAD tool is proposed to verify the interrupt behavior of processors –Automatically generate the hardware and software for verification –Automatically verify the processor –The generated hardware is very small –Highly focused verification cases –Less simulation cycles – 4329 verification cases – Less than cycles of RTL simulation – 424 seconds in real time