DASAR DIGITAL & SIMULATOR XILINX Minggu 2 & 3. Gerbang-gerbang digital AND ABY 000 010 100 111 OR ABY 000 011 101 111 NOT AY 01 10.

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Presentation transcript:

DASAR DIGITAL & SIMULATOR XILINX Minggu 2 & 3

Gerbang-gerbang digital AND ABY OR ABY NOT AY 01 10

NAND ABY NOR ABY XOR ABY XNOR ABY

Rangkaian terintegrasi  Half adder Half adder dengan 4 gerbang Half adder dengan 2 gerbangn logika Tabel kebenaran half adder InputOutput ABSC Ket : S = Sum, hasil jumlah C = Carry, sisa hasil jumlah

Full adder Tabel kebenaran full adder Input Output ABCCS

Half adder dari 2 rangkaian

SIMULATOR XILINX Perancangan rangkaian digital : State diagram Hardware Description language (HDL)  ABEL & VHDL Schematic Editor Dipelajari :  mulai projek baru  menggambarkan skematik rangkaian digital  simulasi rangkaian

Mulai projek : Klik ikon projek manager sehingga bisa masuk ke Xilinx Projek manager.

Disain rangkaian digital File  New Project

Schematic Editor Klik Schematic editor untuk memulai menggambar rangkaian

Gambar rangkaian : Options  Create Netlist Options  integrity test Simulasi

Signal  Add Signals Signal  Add Stimulators

View  Main toolbox Hasil simulasi gerbang AND

Tugas :  Simulasikan gerbang digital dasar!