1. Today’s Lab Start working with Xilinx
[pronounced: Zy-links] ISE design suite
Create new project
Enter code
Synthesize code
Simulate code
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

2. Half Adder AND to arrive at Carry XOR to arrive at Sum A B S C Inputs
Outputs A B S C 1
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

3. Half Adder Verilog Code
module half_adder (A, B, Sum, C_out);
input A, B;
output Sum, C_out;
xor (Sum, A, B);
and (C_out, A, B);
endmodule
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

4. Creating a New Project
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

5. New Project Options
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

6. Create the Verilog file
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

7. Synthesize Verilog File
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

8. Schematic view
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012

9. Simulation Waveforms
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012