Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must.

Slides:



Advertisements
Similar presentations
CMOS Logic Circuits.
Advertisements

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
CH14 BIPOLAR DIGITAL CIRCUITS The Ideal BJT Transistor Switch
TTL (Transistor Transistor Logic).  Transistor Transistor logic or just TTL, logic gates are built around only transistors.  TTL was developed in 1965.
1 Voltage Translation Clamps ASIA MARKETING DEVELOPMENT Samuel Lin Standard Logic 2012/Q1.
Digital Electronics Logic Families TTL and CMOS.
Electronic memory & logic devices. Solid State Physics N N P P +- Transistors And diodes Logic gates Memory devices : Flip flops Flip Flop Flip Flop Flip.
Data Acquisition ET 228 Chapter
Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must.
Logic Families and Their Characteristics
Intro to Logic Gates & Datasheets
Electrical and Timing Characteristics of Standard Logic Gates (Lecture #2) ECE 331 – Digital System Design.
CMOS gates Electrical characteristics and timing TTL gates
Voltage Transfer Characteristic for TTL
ALB (Advanced Low-Voltage BiCMOS) Voltage nodes (Vcc) : 3.3V Speed tpd max(ns) : 2 Output Current IOL(mA) : 25 Output Current IOH(mA) : -25 Current Into.
EE365 Adv. Digital Circuit Design Clarkson University Lecture #4
Programmable logic and FPGA
Electrical and Timing Characteristics of Standard Logic Gates (Lecture #2) ECE 301 – Digital Electronics.
Microelectronic Circuits - Fourth Edition Sedra/Smith 0 Fig Switching times of the BJT in the simple inverter circuit of (a) when the input v 1 has.
UNIT – V CMOS LOGIC: CMOS logic levels, MOS transistors, Basic CMOS Inverter, NAND and NOR gates, CMOS AND-OR-INVERT and OR-AND-INVERT gates, Implementation.
EET 252 Unit 2 Integrated Circuit Technologies
In a not gate, if the input is on(1) the output is off (0) and vice versa.
Component Identification: Digital Introduction to Logic Gates and Integrated Circuits © 2014 Project Lead The Way, Inc.Digital Electronics.
Digital logic families
1 Terminations Chris Allen Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm.
EET 1131 Unit 9 Logic Families
INTEGRATED CIRCUIT LOGIC FAMILY
Logic Families and Their Characteristics
Digital Logic Families PHYS3360/AEP3630 Lecture 26 1.
Fairchild Power Switch Sep, 2004 Power Conversion.
Electrical Characteristics of Logic Gates Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.
Spartan-II Memory Controller For QDR SRAMs Lobby Pitch February 2000 ®
Integrated Circuit Logic Families. Outline  Integrated Circuit Logic Families.
Chapter 4 Logic Families.
Chapter 11 Logic Gate Circuitry.
 Seattle Pacific University EE Logic System Design Standard Gates-1 Logic Chips HD74LS04P HD74LS04P Actual circuit.
® Additional Spartan-XL Features. ® Family Highlights  Spartan (5.0 Volt) family introduced in Jan. 98 —Fabricated on advanced 0.5µ process.
Logic Gates Chapter 6 Subject: Digital System Year: 2009.
IC Logic Families Wen-Hung Liao, Ph.D.
CHAPTER 1 : INTRODUCTION
“Supporting the Total Product Life Cycle”
Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.
John Moulton & Art Sibbach 5/19/08
Bi-CMOS Prakash B.
Electrical Characteristics of ICs Part 3 Last Mod: January 2008  Paul R. Godin.
Electrical Characteristics of IC’s Part 2
CH31 Chapter 3 Logic Gates By Taweesak Reungpeerakul.
EE Electronics Circuit Design Digital Logic Gates 14.2nMOS Logic Families 14.3Dynamic MOS Logic Families 14.4CMOS Logic Families 14.5TTL Logic.
Topic 1 Topic 1 Objectives Topic 2 Topic 2 Topic 3 Topic 3 Topic 4 Topic 4Menu.
AND Gate Inputs Output Input A (Switch) Input B (Switch) Output Y (Lamp) 0 (Open) 0 (OFF) A B Lamp.
Physical Properties of Logic Devices Technician Series Created Mar
CMOS Technologie 1° - Short presentation : What does CMOS mean ? What component is it ? Few pictures display. 2° - The different characteristics of the.
Electrical Characteristics of Logic Gates
Logic Families.
Chapter 06 Logic Gate Circuitry.
EI205 Lecture 3 Dianguang Ma Fall, 2008.
Digital Design Jeff Kautzer Univ Wis Milw.
Power Semiconductor Systems I
NAME:AKSHAY PATEL
Topics Off-chip connections..
Digital Logic Families
Lecture No. 7 Logic Gates Asalam O Aleikum students. I am Waseem Ikram. This is the seventh lecture in a series of 45 lectures on Digital Logic Design.
CSE221- Logic Design, Spring 2003 Logic Technology
XC9500XL New 3.3v ISP CPLDs.
AWIM Series Lawndale High School Experiment 6 Dec, 2017
EP SELF RM TERMINATED STEP UP TO COST SAVINGS SPACE SAVINGS
Circuits using NMOS and PMOS enhancement mode FETs
Component Identification: Digital
Sales Training Presentation
FAN3180 Single 2-A Gate Driver with 3.3-V 15-mA LDO
Presentation transcript:

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/011 THE WORLD OF LOGIC FAMILIES Source: TI LVXVCXLCX Tiny Logic VCXLCXVCXLCX VHC/ VHCT FST

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/012 Source: Insight Onsite WORLDWIDE LOGIC TAM & MARKET SHARE

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/013 PRODUCT LIFE CYCLE Source: TI LS/S SCAN TTL ABT VCX VHC/VHCT FACT FAST/FASTr/ALS HC/HCT ECL IntroductionGrowthMaturitySaturationDeclining CD4000/74C AS TinyLogic LVX/LCX/LVT ALVT FST Source: Fairchild

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/014 Bipolar families : Saturation or decline phase 5V CMOS families : maturity or saturation phase except for AHC/AHCT and VHC/VHCT FAMILY RECOMMANDATION Recently discontinued (LTB = 30/04/01) Not recommended for new designs Not recommended for new designs new designs

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/015 BiCMOS families : maturity phase for ABT growth phase for LVT (3.3V) and ALVT (2.5V). FAMILY USED RECOMMANDATION new designs 3.3V CMOS families : growth phase. Pay attention with FCT3 New designs

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/016 WHO MAKES WHAT ? x x

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/017 LOGIC VENDOR PARTNERSHIPS Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/018 FAMILY PERFORMANCE POSITIONING Source: Texas.Instr.

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/019 Source: Fairchild. FAMILY PERFORMANCE POSITIONING

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0110 LOW-VOLTAGE LOGIC COMPARISON Source: Fairchild IDT Hitachi, IDT TI FSC, TOSH ON, STm, Pericom FSC, TOSH ON, STm, Pericom ON

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0111 LOW-VOLTAGE MARKET COVERAGE Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0112 LOGIC MIGRATION Source: Fairchild Source: Philips

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0113 LOGIC MIGRATION Source: Fairchild

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/ Volt Tolerant I/Os ADVANCED-LOGIC FEATURE LIST Output Series Termination Resistors (damping resistor) Live Insertion (Power-up/Power-down 3-State, I OFF) Bus Hold LVC, LVT, ALVT, LCX 5 V TTL bus 5 V bus ABT, ALVT, LVC, LVT ABT, ALVC, ALVT, LVC, LVT, LCX ABT, ALVC, ALVT, LVC, LVT, LCX, VCX

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0115 Small package options: Less board space needed Optimized PCB layout: Simplified routing Reduced EMI noise: Better routing possibilities Enhancing ASIC functionality: Quick fixes WCSP - smaller package: Enhanced thermal and electrical performance Benefits LITTLE LOGIC (SINGLE & DUAL GATE) Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0116 TinyLogic TM HS and HST families drop-in replacements for High-Speed (TC7Sxx) UHS is the fastest available single gate logic All 5-lead functions available in either SOT-23 or SC70 packaging Six lead latches, flip/flops and dual buffers in unique six lead SC70 pkg. Tiny ’00 Quad-gate ’00 HS VHC-like CMOS inputs 5V designs 2mA Drive <25ns max at 5v HST VHCT-like TTL inputs 5V designs 2mA Drive <30ns max at 5v UHS LCX-like CMOS inputs 3V designs ( V Vcc) 24mA Drive <5.2ns max at 5v 5v over-voltage tolerant I/O FS FST-like 3V designs ( V Vcc) <6 ns enable and disable Low Ron < 7 Ohms High Bandwidth >250 MHz Source: Fairchild

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0117 † Symbol or red indicates C i = 30 pF LITTLE LOGIC FEATURES Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0118 FAIRCHILD’S LOW VOLTAGE LOGIC ROADMAP 74LVXxxx 74LCXxxx74VCXxxx Next Gen 74LVTxxx74ALVTxxx 74HCxxx Vcc : 2-6.0V Tpd : 23nS Ioh/Iol : 6mA Vcc : 2-3.6V Tpd : 7.0nS Ioh/Iol : 4mA Vcc : 2-3.6V Tpd : 4.5nS Ioh/Iol : 24mA Vcc : V Tpd : 4nS Ioh/Iol : 2-4mA Vcc : V Tpd : 2.5nS Ioh/Iol : 24mA Vcc : V Tpd : 3.5nS Ioh/Iol : -32/64mA Vcc : V Tpd : 2.5nS Ioh/Iol : -32/64mA Current Drive (Ioh/Iol) 0 mA 64 mA Supply Voltage (Vcc) 7.0 V1.0 V Source: Fairchild

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0119 SOT23-5 package outline 2.9 mm 2.84 mm SC70 pkg outline 2.0 mm 2.1 mm Pitch Length WidthArea Height SOT23-5 (M5) SC70-5 (P5) LITTLE LOGIC PACKAGES

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0120 LOGIC PACKAGING LIFE CYCLE Source: Fairchild

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0121 PACKAGING OPTIONS Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0122 SELECTING A LOGIC FAMILY Source: TI

Séminaire CNES : CI Logiques & Interfaces THALES RESEARCH & TECHNOLOGY FRANCE Information included in this document is the property of THALES. It must not be disclosed without the prior written consent of THALES RESEARCH & TECHNOLOGY. Modèle trtco V /10/0123 LOW VOLTAGE DECISION TREE