Introduction to CMOS VLSI Design Introduction Manoel E. de Lima David Harris - Harvey Mudd College

CMOS VLSI Design0: IntroductionSlide 2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale Integration (VLSI): very many  Complementary Metal Oxide Semiconductor –Fast, cheap, low power transistors  Today: How to build your own simple CMOS chip –CMOS transistors –Building logic gates from transistors –Transistor layout and fabrication  Rest of the course: How to build a good CMOS chip

CMOS VLSI Design WHY VLSI DESIGN? Money, technology, civilization

CMOS VLSI Design Annual Sales transistors manufactured in million for every human on the planet

CMOS VLSI Design Digression: Silicon Semiconductors  Modern electronic chips are built mostly on silicon substrates  Silicon is a Group IV semiconducting material  crystal lattice: covalent bonds hold each atom to four neighbors

CMOS VLSI Design0: IntroductionSlide 6 Silicon Lattice  Transistors are built on a silicon substrate  Silicon is a Group IV material  Forms crystal lattice with bonds to four neighbors

CMOS VLSI Design0: IntroductionSlide 7 Dopants  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  Group V: extra electron (n-type)  Group III: missing electron, called hole (p-type)

CMOS VLSI Design0: IntroductionSlide 8 p-n Junctions  A junction between p-type and n-type semiconductor forms a diode.  Current flows only in one direction

CMOS VLSI Design A Brief History Invention of the Transistor Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor (3 terminal devices) Shockley, Bardeen and Brattain at Bell Labs

CMOS VLSI Design A Brief History, contd..  1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor smithsonianchips.si.edu/ augarten/ Kilby’s IC

CMOS VLSI Design A Brief History, contd. First Planer IC built in Intel Pentium 4  processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society

CMOS VLSI Design  1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle  1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel bit SRAMIntel bit  Proc

CMOS VLSI Design Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates

CMOS VLSI Design Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration First patent in the ’20s in USA and Germany Not widely used until the ’60s or ’70s

CMOS VLSI Design0: IntroductionSlide 15 nMOS Transistor  Four terminals: gate, source, drain, body  Gate – oxide – body stack looks like a capacitor –Gate and body are conductors –SiO 2 (oxide) is a very good insulator –Called metal – oxide – semiconductor (MOS) capacitor –Even though gate is no longer made of metal

CMOS VLSI Design0: IntroductionSlide 16 nMOS Operation  Body is commonly tied to ground (0 V)  When the gate is at a low voltage: –P-type body is at low voltage –Source-body and drain-body diodes are OFF –No current flows, transistor is OFF

CMOS VLSI Design0: IntroductionSlide 17 nMOS Operation Cont.  When the gate is at a high voltage: –Positive charge on gate of MOS capacitor –Negative charge attracted to body –Inverts a channel under gate to n-type –Now current can flow through n-type silicon from source through channel to drain, transistor is ON

CMOS VLSI Design0: IntroductionSlide 18 pMOS Transistor  Similar, but doping and voltages reversed –Body tied to high voltage (V DD ) –Gate low: transistor ON –Gate high: transistor OFF –Bubble indicates inverted behavior

CMOS VLSI Design0: IntroductionSlide 19 Power Supply Voltage  GND = 0 V  In 1980’s, V DD = 5V  V DD has decreased in modern processes –High V DD would damage modern tiny transistors –Lower V DD saves power  V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

CMOS VLSI Design0: IntroductionSlide 20 Transistors as Switches  We can view MOS transistors as electrically controlled switches  Voltage at gate controls path from source to drain

CMOS VLSI Design Transistors LevelSymbolSwitch Conditions Strong 11P-switch gate=0, source=V dd Weak 11N-switch gate=1, source=V dd Strong 00N-switch gate=1, source=V ss Weak 00P-switch gate=0, source=V ss High impedanceZN-switch gate=0, or P-switch gate=1 0: IntroductionSlide 21 Input 0 Output Good 0 Input 1 Output poor 1 Input 0 Output poor 0 Input 1 Output good 1

CMOS VLSI Design0: IntroductionSlide 22 Input 0 Output Good 0 Input 1 Output poor 1 Input 0 Output poor 0 Input 1 Output good 1

CMOS VLSI Design0: IntroductionSlide 23 CMOS Inverter AY 0 1

CMOS VLSI Design0: IntroductionSlide 24 CMOS Inverter AY 0 10

CMOS VLSI Design0: IntroductionSlide 25 CMOS Inverter AY 01 10

CMOS VLSI Design CMOS Inverter Vin VoutVddVss C load Q1 Q2 IdIdIdId 1- Vin = Vdd Análise do circuito: Vdd=+5V 0V Vout Roff Ron Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Ids.Roff+Vout => Vout = Vdd-Ids.Roff 0V Ids Ron < 1 Kohms Roff Kohms Ids é pequeno, mas Roff é bastante grande

CMOS VLSI Design CMOS Inverter Note que V h = 5V, V L = 0V, e que I ds = 0A. Isto significa que não existe praticamente dissipação de potência.

CMOS VLSI Design CMOS Inverter +5V GND V ih =´1´ R +5V GND Out I ol I il In V ol (max) V il (max) Tempo (seg) Tensão(V) V il (max) Nível ´0´ Capacitor carregado (´1´) Transistor conduz R on  1 K  Transistor não conduz R on  1 K 

CMOS VLSI Design CMOS Inverter Vin VoutVddVss C load Q1 Q2 IdIdIdId 2- Vin = 0V Análise do circuito: Vdd=+5V 0V Vout Ron Roff Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Vout+Ids.Ron => Vout = Vdd-Ids.Ron Vdd=5VIds Ron < 1 Kohms Roff Kohms Ids é muito pequeno

CMOS VLSI Design CMOS Inverter Note que V h = 5V, V L = 0V, e que I ds = 0A. Isto significa que não existe praticamente dissipação de potência.

CMOS VLSI Design CMOS Inverter +5V GND V il =0 R +5V GND Out I oh I ih In V oh (min) V ih (min) Tempo (seg) Tensão(V) V ih (min) Nível ´1´ Capacitor X Transistor não conduz R off  Transistor conduz R on  1 K 

CMOS VLSI Design0: IntroductionSlide 32 CMOS NAND Gate ABY

CMOS VLSI Design0: IntroductionSlide 33 CMOS NAND Gate ABY

CMOS VLSI Design0: IntroductionSlide 34 CMOS NAND Gate ABY

CMOS VLSI Design0: IntroductionSlide 35 CMOS NAND Gate ABY

CMOS VLSI Design0: IntroductionSlide 36 CMOS NAND Gate ABY

CMOS VLSI Design Lógica Combinacional  Porta NAND saída A B A B P P N N Vcc (‘1’) GND (‘0’) saída Vcc GND ABAB Saída GND ABCnABCn A BC n Vcc Porta NAND de n-entradas (A+B) (A B) Dual Lógico

CMOS VLSI Design0: IntroductionSlide 38 CMOS NOR Gate ABY

CMOS VLSI Design Lógica Combinacional  Porta NOR A B N N P Vcc (‘1’) GND (‘0’) saída P Vcc GND ABAB saída Saída Vcc nABCnABC A B C n GND saída A B (A B) (A+B) Dual Lógico

CMOS VLSI Design0: IntroductionSlide 40 3-input NAND Gate  Y pulls low if ALL inputs are 1  Y pulls high if ANY input is 0

CMOS VLSI Design0: IntroductionSlide 41 Summary  MOS Transistors are stack of gate, oxide, silicon  Can be viewed as electrically controlled switches  Build logic gates out of switches