TPC DETECTOR SEGMENTATION OF THE READOUT PLANE LATERAL VIEW OF THE TPC 18 trapezoidal sectors Inner chamber 5504 pads Outer chamber 10332 SEGMENTATION OF THE READOUT PLANE LATERAL VIEW OF THE TPC 500cm 83cm 248cm 88us 1MIP = 4.8 fC = 3 x104 e Dynamic : 30 MIP S / N = 30:1 Luciano Musa - CERN

TPC FEE: MOUNTING SIDE VIEW 128 channels Front End Card (FEC) Capton Cable 140mm 190mm 36 trapezoidal sectors Inner chamber Outer chamber FEC C1 : 18 FECs C6 : 20 FECs C4 : 20 FECs C3 : 18 FECs C2 : 25 FECs FRONT VIEW C5 : 20 FECs Here you can see how the FECs are grouped and connected to the pad plane. The FEC connected to the pad plane via 6 capton cables in this side view. And in the front view the repartition of the a TPC sectors in 5 regions and the related number of FEC for each of these regions. Luciano Musa - CERN

GLOBAL ARCHITECTURE Each TPC Sector is served by 6 Readout Subsystems FEE ARCHITECTURE GLOBAL ARCHITECTURE Each TPC Sector is served by 6 Readout Subsystems FEC COOLING 1 FEC 128 ch LOW VOLTAGE POWER SUPPLY UX CRX 2 FEC 128 ch CONFIG. & READOUT NETWORK (100 MB / s) FEC 128 ch DATA PROC. DATA MEMORY DAQ INT (DDL-SIU) CONF. & R/O DCS NETWORK DCS INT (PROFIB, ETHER, ...) 25 MON. & CTRL BOARD CONTROLLER FEC 128 ch TRIGGER INT (TTC-RX) From the readout point of view each TPC sector is subdivided in 5 radial regions: 2 in the inner chamber and 3 in the outer chamber. The basic unit is a system which serves one of this Sector regions: one fifth of a TPC sector. In other words each of the 36 TPC sectors is served by 5 readout subsystems. This sub-sector readout system consists of up to 32 FEC (described in the previous slide). The precise number of FEC in the readout system depends on the radial position of the TPC sector served, and varies from 20 (for the innermost region) to 32 for the outermost region (I must get from: Danilo – Rudi – Hans – Rainer the new organization of FEC). The FEC are controlled, via a bi-directional bus, by a Readout Control Unit which interfaces the FECs to the rest of the acquisition and control systems of the experiment: to the DAQ (RORC) via the DDL, to the DCS via a serial link (Profi-bus – from Roberto the bandwidth). and to the Triggger via the TTC system (look your notes to be more precise on the trigger interface). All the standard acquisition operations (configuration of the front-end electronics and data readout) are performed via the DDL and bi-directional readout bus. It has a bandwidth of 160 Mbyte / sec (or 320 MB / sec ??). The slow control link can access all the parameters which monitor the correct functioning of the FEE: board temperatures, low voltages, warning and error conditions. The local slow control link, which can also spy the readout bus, reports any anomaly to the RCU, that apart reporting to the central DCS, can also take some immediate action. I would like to mention that indeed the local slow control has a complete access to the FECs and through it one can completely configure the FECs and the RCS, and perform the readout. This feature will be used during the production test, the installation, or in standalone mode, but not during the operation of the detector in the physic srun. In the RCU is also performed a data compression. That depends on if and hoe the data is going to be further performed by the L3 farm. Essentially there is the possibility of performing a loss-less data compression (Hoffmann or arithmetic) or the extraction of the cluster features. With loss-less data compression a factor 2. That the reason for 300 MB/s. RCU Overall TPC: 4356 Front End Card 216 Readout Control Unit Luciano Musa - CERN

128-CHANNEL FRONT-END CARD FEC COOLING LV SUPPLY readout bus connectors control bus connector power supply connector cooling pipe voltage regulators GTL transceivers (back side) current monitoring & supervision ALTROs The signal induced on a pad has a dynamic of 1000 (10 bits) and has to be measured with a resolution of 0.16fC (1000 e) (dynamic: 0.16fC -> 160 fC). Additional information id the total charge seen by a pad over the 88us: Xfc The basic readout chain consists of: A Charge sensitive amplifier, which converts 1000e in 2mV (or 1mV) a shaper amplifier Semi-Gaussian shaper. A low power 10-bit A/D converter running at sampling rate below 10MSPS. A digital circuit to preprocess the digitized signal: subtraction of the baseline, cancellation of the ion tail, and zero suppression. The zero suppressed data is then formatted before to be stored in a multi-event buffer which can contain (accogliere o accomodare) up to 4 events. Data coming from 4096 channels is multiplexed into the DDL which transports the data from the FEE to the DAQ. The basic circuits that compose the basic readout chain are organized in the following way: a chip which incorporates the amplifier and shaper for 16 channels; baseline is a stand-alone commercial ADC (single or dual); however I will show later that we are now looking at the possibility of integrating the ADC into the digital chip. the digital chip integrates 8 channels. This components are physically incorporated in a FEC which contains 128 channels seating at a few centimeters from the PAD plane to which is connected by 6 capton cables. One of the most tight requirements is represented by the power consumption: each 2mW represents indeed 1kW of power to be extracted by the cooling system (active cooling system). Temperature stability of 0.1C. In this concern should be noted that the readout chain process the TPC signal for 88us at a maximum rate of (L1) 200 Hz. Therefore it has a duty cycle below < 2% and makes the digital power consumption negligible. Shaping Amplifiers Kapton cables to TPC Luciano Musa - CERN

FEE PARAMETERS TO BE MONITORED AND/OR CONTROLLED FRONT_END CARD FEE PARAMETERS TO BE MONITORED AND/OR CONTROLLED (PRELIMINARY !) Front End Card (FEC) Temperature: 1 value (10 bits) / FEC R Volt. Reg. State (on/off): 8 values (8 bits) / FEC R/W Power Switches (on/off): 2 values (2 bits) / FEC R/W Analogue Voltage: 1 value (10 bits) / FEC R Digital Voltage: 1 value (10 bits) / FEC R Status / Error Register: 1 value (64 bits) / FEC R/W Readout Control Unit (RCU Volt. Reg. State (on/off): 4 values (8 bits) / FEC R/W Power Switches (on/off): 1 values (2 bits) / FEC R/W Digital Voltages: 2 value (20 bits) / FEC R Events that could damage the FEE components are hardware protected. The FEE cooling and LV POWER SUPPLY have their independent set of sensors. The signal induced on a pad has a dynamic of 1000 (10 bits) and has to be measured with a resolution of 0.16fC (1000 e) (dynamic: 0.16fC -> 160 fC). Additional information id the total charge seen by a pad over the 88us: Xfc The basic readout chain consists of: A Charge sensitive amplifier, which converts 1000e in 2mV (or 1mV) a shaper amplifier Semi-Gaussian shaper. A low power 10-bit A/D converter running at sampling rate below 10MSPS. A digital circuit to preprocess the digitized signal: subtraction of the baseline, cancellation of the ion tail, and zero suppression. The zero suppressed data is then formatted before to be stored in a multi-event buffer which can contain (accogliere o accomodare) up to 4 events. Data coming from 4096 channels is multiplexed into the DDL which transports the data from the FEE to the DAQ. The basic circuits that compose the basic readout chain are organized in the following way: a chip which incorporates the amplifier and shaper for 16 channels; baseline is a stand-alone commercial ADC (single or dual); however I will show later that we are now looking at the possibility of integrating the ADC into the digital chip. the digital chip integrates 8 channels. This components are physically incorporated in a FEC which contains 128 channels seating at a few centimeters from the PAD plane to which is connected by 6 capton cables. One of the most tight requirements is represented by the power consumption: each 2mW represents indeed 1kW of power to be extracted by the cooling system (active cooling system). Temperature stability of 0.1C. In this concern should be noted that the readout chain process the TPC signal for 88us at a maximum rate of (L1) 200 Hz. Therefore it has a duty cycle below < 2% and makes the digital power consumption negligible. Luciano Musa - CERN