TOPIC : Reduced Ordered Binary Decision Diagrams UNIT 1: Modeling Digital Circuits Module 1 : Functional Modeling.

Slides:



Advertisements
Similar presentations
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Advertisements

CDA 3100 Recitation Week 10.
Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection
Planning based on Model Checking Dept. of Information Systems and Applied CS Bamberg University Seminar Paper Svetlana Balinova.
1 Combinational Logic Design&Analysis. 2 Introduction We have learned all the prerequisite material: – Truth tables and Boolean expressions describe functions.
Combinational Circuits. Analysis Diagram Designing Combinational Circuits In general we have to do following steps: 1. Problem description 2. Input/output.
Heaps1 Part-D2 Heaps Heaps2 Recall Priority Queue ADT (§ 7.1.3) A priority queue stores a collection of entries Each entry is a pair (key, value)
CS-2852 Data Structures LECTURE 11 Andrew J. Wozniewicz Image copyright © 2010 andyjphoto.com.
Digital Logic Design Lecture 27.
Nonlinear & Neural Networks LAB. CHAPTER 19 State Machine Design with SM charts 19.1 State Machine Charts 19.2 Derivation of SM Charts 19.3 Realization.
Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits using Binary Moment Diagrams” by.
Binary Decision Diagrams. ROBDDs Slide 2 Example Directed acyclic graph non-terminal node terminal node What function is represented by the graph?
Binary Decision Diagrams1 BINARY DECISION DIAGRAMS.
08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:
ECE Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
 2001 CiesielskiBDD Tutorial1 Decision Diagrams Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA
TOPIC : Truth tables and Primitive Cubes
Copyright © Cengage Learning. All rights reserved. CHAPTER 2 THE LOGIC OF COMPOUND STATEMENTS THE LOGIC OF COMPOUND STATEMENTS.
Function: Definition A function is a correspondence from a first set, called the domain, to a second set, called the range, such that each element in the.
Digital Computer Design Fundamental
Digitaalsüsteemide verifitseerimise kursus1 Formal verification: BDD BDDs applied in equivalence checking.
Learning Outcome By the end of this chapter, students are expected to understand a few elementary components in digital system Decoder Multiplexer Demultiplexer.
Circuit, State Diagram, State Table
TOPIC : Introduction to Functional Modeling UNIT 1: Modeling Digital Circuits Module 1 : Functional Modeling.
Identifying Reversible Functions From an ROBDD Adam MacDonald.
Truth Table-Based Testing Generating test cases when the test model is a truth table Reading: Binder Chapter 6.
TODAY YOU ARE LEARNING to explain why data is represented in computer systems in binary form 2. to understand and produce simple logic diagrams.
©Ian Sommerville 2000 Software Engineering, 6th edition. Chapter 20 Slide 1 Defect testing l Testing programs to establish the presence of system defects.
Graph Theory Topics to be covered:
Digital Systems I EEC 180A Lecture 4 Bevan M. Baas.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
ACOE1611 Combinational Logic Circuits Reference: M. Mano, C. Kime, “Logic and Computer Design Fundamentals”, Chapter 2.
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda Rolf Drechsler Alex Orailoglu Computer Science & Engineering Dept. University.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
1 5. Abstract Data Structures & Algorithms 5.1 Data Structure Fundamentals.
DESIGN OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.
1 State Reduction Goal: reduce the number of states while keeping the external input-output requirements unchanged. State reduction example: a: input 0.
Functional Modeling.
1 Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits with Binary Moment Diagrams” by Randal.
BDDs1 Binary Tree Representation The recursive Shannon expansion corresponds to a binary tree Example: Each path from the root to a leaf corresponds to.
Write a function rule for a graph EXAMPLE 3 Write a rule for the function represented by the graph. Identify the domain and the range of the function.
Heaps © 2010 Goodrich, Tamassia. Heaps2 Priority Queue ADT  A priority queue (PQ) stores a collection of entries  Typically, an entry is a.
Binary Decision Diagrams Prof. Shobha Vasudevan ECE, UIUC ECE 462.
1-6 and 1- 7: Relations and Functions Objectives: Understand, draw, and determine if a relation is a function. Graph & write linear equations, determine.
IT 60101: Lecture #121 Foundation of Computing Systems Lecture 13 Trees: Part VIII.
BDD-based Synthesis of Reversible Logic for Large Functions Robert Wille Rolf Drechsler DAC’09 Presenter: Meng-yen Li.
TOPIC : State Tables UNIT 1: Modeling and Simulation Module 4 : Modeling Sequential Circuits.
Network Topology Deals with a circuit model called graph, which is a collection of line segments called branches and points called nodes Circuit diagram.
Binary search tree. Removing a node
Chapter 2.3 Binary Logic.
Heaps © 2010 Goodrich, Tamassia Heaps Heaps
Heaps 9/13/2018 3:17 PM Heaps Heaps.
KS4 Electricity – Electronic systems
KS4 Electricity – Electronic systems
Digital Signals Digital Signals have two basic states:
Basic Digital Logic Basic Gates
Binary Search Tree In order Pre order Post order Search Insertion
Part-D1 Priority Queues
Heaps 11/27/ :05 PM Heaps Heaps.
© 2013 Goodrich, Tamassia, Goldwasser
Digital Logic.
KS4 Electricity – Electronic systems
DESIGN OF SEQUENTIAL CIRCUITS
DIGITAL ELECTRONICS B.SC FY
A logic function f in n inputs x1, x2, ...xn and
Example: Verification
Chapter 6 Vocabulary Input Output Function
A logic function f in n inputs x1, x2, ...xn and
Copyright © Cengage Learning. All rights reserved.
Heaps 9/29/2019 5:43 PM Heaps Heaps.
Presentation transcript:

TOPIC : Reduced Ordered Binary Decision Diagrams UNIT 1: Modeling Digital Circuits Module 1 : Functional Modeling

Binary Decision diagram(BDD) Is there any other way to reduce the number of entries for describing the circuit? ◦ Yes, BDD. A graph model of the function of a circuit. One can determine the output by simple graph traversal procedure. There are decision nodes and terminal nodes. Each decision node will have two child nodes: 0-child, 1-child. At every node, follow the left or the right branch depending upon the value (0 or 1) of the corresponding decision node.

Example The dotted lines represent a 0-child and solid lines represent 1- child According to the given inputs traverse down to the exit terminal. Ex: x1=1,x2=0,x3=1 Since x1=1 select the solid line to x2, then x2=0 so select the dotted line to x3, and since x3=1 chose the solid line from x3 which leads to the exit terminal and reflects the output as 1.

How to construct BDD?? Start the tree with one of the inputs, say x1. X1 can be 0 or 1, so map these two possible cases to the next input, say x2. Follow the same procedure for x2 and all the other inputs. Follow till you reach the exit terminal (no more inputs to map). Point the exit terminals to 0 or 1 looking at truth table. Binary decision diagram is built. This diagram can be simplified leading to reduction in the input entries.

Reduced Ordered BDD (ROBDD) Observe the complete BDD of the example from exit terminals. Both branches from the left most node x3 results in the same value 1, we remove this node and replace it by an exit branch with value 1. Similarly the next node x3 can be replaced by 0. Reduced BDD

ROBDD contd… Observe the two left most exit terminals ◦ they are the inverted values of its parent node, so the left x2 node can be replaced by x2. Similarly the node x3 which is to the left of x2 can be replaced by x3 The two right most exit terminals can be removed, since they are the same as their parent node. The dot represents the inverter.