1. Digital Systems I EEC 180A Lecture 4 Bevan M. Baas

2. This circuit schematic shows all 8 minterms “present” for a 3-input combinational logic function In practice, all possible minterms would never all be present in a circuit (do you see why?) There is one possible minterm for each row in the truth table m1m1 m0m0 m2m2 m3m3 m4m4 m5m5 m6m6 m7m7 Z Minterm Example

3. By construction, one and only one minterm is active (equals 1) at any point in time m1m1 m0m0 m2m2 m3m3 m4m4 m5m5 m6m6 m7m7 0 0 0 0 0 0 0 1 0 0 1 Z 1

4. Minterm Example By construction, one and only one minterm is active (equals 1) at any point in time m1m1 m0m0 m2m2 m3m3 m4m4 m5m5 m6m6 m7m7 0 0 1 0 0 0 0 0 0 1 1 Z 1

5. Minterm Example Z = m 0 + m 1 + m 7 To implement an expression, a circuit is built with only the present minterm(s) The output can be 1 only when one of the present minterms forces the output to 1 m1m1 m0m0 m2m2 m7m7 0 1 1 Z 0 0 0 0

6. Minterm Example Z = m 0 + m 1 + m 7 To implement an expression, a circuit is built with only the present minterm(s) The output can be 1 only when one of the present minterms forces the output to 1 m1m1 m0m0 m2m2 m7m7 1 1 1 Z 0 1 0 1

7. Minterm Example Z = m 0 + m 1 + m 7 Of course gate inputs can not be left unconnected (unspecified). There are two solutions: –Tie unused inputs to a value that disables those inputs. For an OR gate, inputs would be tied to 0 (or False or Gnd) –The best solution is to simplify the gate. In this example, the 8-input OR gate is simplified to a 3-input OR gate m1m1 m0m0 m2m2 m7m7 1 1 1 Z 0 1 0 1