Computer Architecture Lecture 2 Abhinav Agarwal Veeramani V.

Quick Recap Various metrics in design of processor The interface & internal structure Instruction Set Architecture  Assembly instructions  Instruction encoding add r1, r2, r

Outline RISC Multi-cycle execution Pipelining

Reduced Instruction Set Computer (RISC) Limited no. of instructions Fixed Length Simple to decode Easier to implement in hardware Prevalent in all commercial processors at the core level Counterpart – C(omplex)ISC  Intel processors  Multi-operation instructions  Still Intel processors have switched to RISC at second level

Execution Cycle of a RISC Instruction Five main phases of Instruction Lifecycle 1. IF: Instruction Fetch Read Instruction Memory at PC Bring the instruction into the CPU 2. ID/RF: Instruction Decode/Register Fetch Translate the opcode of the instruction to appropriate control signals No. of operands Registers clearly specified in instruction code Fetch operand values from the registers

Execution Cycle of a RISC Instruction 3. EX: ALU computation  Activate appropriate functional unit – Adder, Multiplier, Divider, Logical Unit  Why no Subtracter? 4. MEM: Memory Operation Load/Store data from/to Data Memory 5. WR: Register Write Write the final result value into register

A Picture speaks a thousand words

Multi Cycle Execution Cycle Per Instruction (CPI) Kinds of Implementation: 1. One cycle for each stage  Cycle time determined by longest stage  CPI = ? 2. Combine all stages into a single cycle  Cycle time determined by worst case instruction  CPI = 1

Execution Snapshot: Cycle 1IF PC AddressInstr 00000Mov r2, 2A 00001Mov r3, Add r1,r2,r Store r1,0(r4) 00100XXXX 00101XXXX

Execution Snapshot: Cycle 2ID/RF Add r1, r2, r PC AddressInstr 00000Mov 00001Mov 00010add 00011Store 00100XXXX 00101XXXX RegData r112 H r22A H r312 H r400 H r501 H

Execution Snapshot: Cycle 3EX RegData r112 H r22A H r312 H r400 H r501 H PC AddressInstr 00000Mov 00001Mov 00010add 00011Store 00100XXXX 00101XXXX Adder 122A Add r1, r2, r3

Execution Snapshot: Cycle 4MEM PC AddressInstr 00000Mov 00001Mov 00010add 00011Store 00100XXXX 00101XXXX Adder 122A ?? RegData r112 H r22A H r312 H r400 H r501 H Add r1, r2, r3

Execution Snapshot: Cycle 5WB PC AddressInstr 00000Mov 00001Mov 00010add 00011Store 00100XXXX 00101XXXX Adder RegData r13C H r22A H r312 H r400 H r501 H Add r1, r2, r3

Execution Snapshot: Cycle 1IF PC AddressInstr 00000Mov 00001Mov 00010add 00011Store 00100XXXX 00101XXXX store r1, 0(r4)

Instruction Execution Timeline Sequential Execution Low utilization of functional units Alternative ? IFID/ RF EXME M WB IFID/ RF EXME M IFID/ RF EXME M WB Instruction Execution Timeline add r1, r2, r3 store r1, 0(r4)

Pipelining: Concept and Example Washing machine, Dryer, Iron source:

Pipelining Concept Remarkable Insight or Common Sense source: Time Savings: Per person0% Overall42%

Implementation of Pipelining in RISC Parallelism in all 5 stages New instruction every cycle Best case scenario IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB Inst Time

Hardware Requirements source:

Problems Data hazards  Dependent Instructions add r1, r2, r3 store r1, 0(r4) Control Hazards  Branches resolution bnz r1, label add r1, r2, r3 label: sub r1, r2, r3 Structural Hazards IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB IFID/RFEXMEMWB

References Wikipedia: CPU Parallelism