Verilog in transistor level using Microwind

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Presentation transcript:

Verilog in transistor level using Microwind

MicroWind Design Tools Example

Schematic Editor

Verilog Compiler

2D 3D Viewer

Simulators

Microwind Main Screen 4/10/2017

Most important icons 4/10/2017

Design Examples Tutorial Lab on MicroWind

MUX implementation In Microwind

MUX 4-1 multiplexer

Behavioral design module mux3( select, d, q ); input[1:0] select; input[3:0] d; output q; reg q; wire[1:0] select; wire[3:0] d; always @( select or d ) begin if( select == 0) q = d[0]; if( select == 1) q = d[1]; if( select == 2) q = d[2]; if( select == 3) q = d[3]; end endmodule module mux4( select, d, q ); input[1:0] select; input[3:0] d; output q; reg q; wire[1:0] select; wire[3:0] d; always @( select or d ) begin case( select ) 0 : q = d[0]; 1 : q = d[1]; 2 : q = d[2]; 3 : q = d[3]; endcase end endmodule

Dataflow: conditional assignment module mux5( select, d, q ); input[1:0] select; input[3:0] d; output q; wire q; wire[1:0] select; wire[3:0] d; assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3]; endmodule

Structural design (1)

Structural design (2) module mux7( select, d, q ); input[1:0] select; input[3:0] d; output q; wire q, q1, q2, q3, q4, NOTselect0, NOTselect1; wire[1:0] select; wire[3:0] d; not n1( NOTselect0, select[0] ); not n2( NOTselect1, select[1] ); and a1( q1, NOTselect0, NOTselect1, d[0] ); and a2( q2, select[0], NOTselect1, d[1] ); and a3( q3, NOTselect0, select[1], d[2] ); and a4( q4, select[0], select[1], d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule

Structural design in MicroWind (3) module mux ( select1, select0, d3, d2, d1, d0, q ); input select1, select0; input d3, d2, d1, d0; output q; wire q1, q2, q3, q4, NOTselect0, NOTselect1; not n1 (NOTselect0, select0); not n2 (NOTselect1, select1); and a1 (q1, NOTselect0, NOTselect1, d0); and a2 (q2, select0, NOTselect1, d1); and a3 (q3, NOTselect0, select1, d2); and a4 (q4, select0, select1, d3); or o1 (q, q1, q2, q3, q4); endmodule // Simulation parameters in Verilog Format // Simulation parameters // select0 CLK 100 100 // select1 CLK 50 50 // d0 CLK 10 10 // d1 CLK 20 20 // d2 CLK 30 30 // d3 CLK 40 40 Verilog Simulation

Layout and simulation Layout Timing

QUESTIONS? THANK YOU