Princess Sumaya University د. بســام كحـالــه Dr. Bassam Kahhaleh 4241 - Digital Logic Design 22343 Computer Organization & Design د. بســام كحـالــه Dr. Bassam Kahhaleh Dr. Bassam Kahhaleh

Princess Sumaya University 4241 - Digital Logic Design 22343 - Computer Organization & Design “Mano” Chapter 4: Register Transfer & Microoperations Dr. Bassam Kahhaleh

Micro-Operations A micro-operation is an elementary operation, performed during one clock pulse, on the information stored in one or more registers. R1 ← R1 + R2 5:20 PM

Register Designation Whole register Portion of a register One bit in a register 5:20 PM

Parallel Register Transfer Unconditional R1 ← R2 Conditional P: R1 ← R2 Simultaneous R1 ← R2 , R3 ← R2 5:20 PM

Bus Transfer R2 ← RA R1 ← RD Consider: Ri ← Rx where i = 0, 1, 2 or 3 x = A, B, C or D 5:20 PM

Bus Transfer 5:20 PM

Bus Transfer 5:20 PM

Bus Transfer 5:20 PM

Bus Transfer 5:20 PM

Bus Transfer 5:20 PM

Bus Transfer 5:20 PM

Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations 5:20 PM

Micro-Operation Types Data Transfer Arithmetic Operations S = A + B Logic Operations Shift Operations 5:20 PM

Time (Propagation) delay = ? Addition S = A + B Time (Propagation) delay = ? 5:20 PM

Time (Propagation) delay = ? Addition S = A + B t = 0 Time (Propagation) delay = ? 5:20 PM

Time (Propagation) delay = ? Addition S = A + B t = t Time (Propagation) delay = ? 5:20 PM

Time (Propagation) delay = ? Addition S = A + B t = 2t Time (Propagation) delay = ? 5:20 PM

Time (Propagation) delay = ? Addition S = A + B t = 3t Time (Propagation) delay = ? 5:20 PM

Time (Propagation) delay = 4 t Addition S = A + B t = 4t Time (Propagation) delay = 4 t 5:20 PM

Addition A ← A + B Flag 5:20 PM

Subtraction A ← A ⎯ B _ A ← A + ( B + 1 ) 5:20 PM

Increment A ← A + 1 5:20 PM

Decrement A ← A ⎯ 1 5:20 PM

Arithmetic 5:20 PM

Arithmetic C2 C1 C0 Function 0 0 0 Y = A + B 0 0 1 Y = A + B + 1 0 1 0 0 0 0 Y = A + B 0 0 1 Y = A + B + 1 0 1 0 0 1 1 Y = A – B 1 0 0 Y = A 1 0 1 Y = A + 1 1 1 0 Y = A – 1 1 1 1 5:20 PM

Arithmetic C2 C1 C0 Function 0 0 0 S = A + B 0 0 1 S = A + B + 1 0 1 0 0 0 0 S = A + B 0 0 1 S = A + B + 1 0 1 0 0 1 1 S = A – B 1 0 0 S = A 1 0 1 S = A + 1 1 1 0 S = A – 1 1 1 1 5:20 PM

Arithmetic Data Control 5:20 PM

Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations AND: S = A Λ B OR: S = A V B XOR: S = A  B AND: S = A • B OR: S = A + B XOR: S = A  B 5:20 PM

Logic 5:20 PM

Logic 5:20 PM

Logic C1 C0 Function 0 0 F = A Λ B 0 1 F =A V B 1 0 F = A  B 1 1 0 0 F = A Λ B 0 1 F =A V B 1 0 F = A  B 1 1 F = A 5:20 PM

Logic C1 C0 Function 0 0 F = A Λ B 0 1 F = A V B 1 0 F = A  B 1 1 0 0 F = A Λ B 0 1 F = A V B 1 0 F = A  B 1 1 F = A 5:20 PM

Logic Data Control 5:20 PM

Micro-Operation Types Data Transfer Arithmetic Operations Logic Operations Shift Operations Logical Shift shl A shr A Arithmetic Shift ashl A ashr A Circular Shift cil A cir A 5:20 PM

Logical & Arithmetic Shift C1 C0 Function 0 0 F = A 0 1 F = shr A 1 0 F = shl A 1 1 F = ashr A 5:20 PM

Logical & Arithmetic Shift C1 C0 Function 0 0 F = A 0 1 F = shr A 1 0 F = shl A 1 1 F = ashr A 5:20 PM

Logical & Arithmetic Shift C1 C0 Function 0 0 F = A 0 1 F = shr A 1 0 F = shl A 1 1 F = ashr A 5:20 PM

Logical & Arithmetic Shift C1 C0 Function 0 0 F = A 0 1 F = shr A 1 0 F = shl A 1 1 F = ashr A 5:20 PM

Logical & Arithmetic Shift C1 C0 Function 0 0 F = A 0 1 F = shr A 1 0 F = shl A 1 1 F = ashr A 5:20 PM

Logical, Arithmetic, & Circular Shift Regular 1 Circular 5:20 PM

Logical, Arithmetic, & Circular Shift C2 C1 C0 Function x 0 0 F = A 0 0 1 F = shr A 0 1 0 F = shl A 0 1 1 F = ashr A 1 0 1 F = cir A 1 1 0 F = cil A 5:20 PM

Arithmetic and Logic Unit (ALU) 5:20 PM

Homework Chapter 4 4-1 4-2 4-3 4-4 4-5 4-6 4-8 4-9 4-10 4-11 4-13 4-15 4-16 4-17 5:20 PM

Homework Mano 4-1 Show the block diagram of the hardware that implements the following register transfer statement: yT2: R2 ← R1, R1 ← R2 5:20 PM

Homework 4-2 The outputs of four registers, R0, R1, R2, and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register, R5. Each register is eight bits long. The required transfers are dictated by four timing variables T0 through T3 as follows: T0: R5 ← R0 T1: R5 ← R1 T2: R5 ← R2 T3: R5 ← R3 The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5. 5:20 PM

Homework 4-3 Represent the following conditional control statement by two register transfer statements with control functions. If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3) 5:20 PM

Homework 4-4 What has to be done to the bus system of Fig. 4-3 to be able to transfer information from any register to any other register? Specifically, show the connections that must be included to provide a path from the outputs of register C to the inputs of register A. 5:20 PM

Homework 4-5 Draw a diagram of a bus system similar to the one shown in Fig. 4-3, but use three-state buffers and a decoder instead of the multiplexers. 4-6 A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. a. How many selection inputs are there in each multiplexer? b. What size of multiplexers is needed? c. How many multiplexers are there in the bus? 5:20 PM

Homework 4-8 Draw the block diagram for the hardware that implements the following statements: x + yz: AR ← AR + BR where AR and BR are two n-bit registers and x, y, and z are control variables. Include the logic gates for the control function. (Remember that the symbol + designates an OR operation in a control or Boolean function but that it represents an arithmetic plus in a microoperation.) 4-9 Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input. xyT0 + T1 + y’T2: AR ← AR + 1 5:20 PM

Homework 4-10 Consider the following register transfer statements for two 4-bit registers R1 and R2. xT: Rl ← R1 + R2 x’T: Rl ← R2 Every time that variable T = 1, either the content of R2 is added to the content of R1 if x = 1, or the content of R2 is transferred to R1 if x = 0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to-1-line multiplexer that selects the inputs to R1. In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1. 5:20 PM

Homework 4-11 Using a 4-bit counter with parallel load and a 4-bit adder, draw a block diagram that shows how to implement the following statements: x: R1 ← R1 + R2 Add R2 to R1 x’y: R1 ← R1 + 1 Increment R1 4-13 Design a 4-bit combinational circuit decrementer using four full-adder circuits. 5:20 PM

Homework 4-15 Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. 4-16 Derive a combinational circuit that selects and generates any of the 16 logic functions listed in Table 4-5. S Cin = 0 Cin = 1 D = A + B (add) D = A + 1 (increment) 1 D = A – 1 (decrement) D = A + B’ + 1 (subtract) 5:20 PM

Homework 4-17 Design a digital circuit that performs the four logic operations of exclusive OR, exclusive-NOR, NOR, and NAND. Use two selection variables. Show the logic diagram of one typical stage. 5:20 PM