Towards a Scalable and Reliable Wireless Network-on-Chip 4/7/2017 Towards a Scalable and Reliable Wireless Network-on-Chip Amlan Ganguly, Ph.D School of EECS, Washington State University Template C Plain-crimson-bright

4/7/2017 Outline Introduction Multi-core & Network-on-Chip (NoC) paradigm Performance limitations of conventional planar NoCs Alternative interconnect technology Wireless NoC (WiNoC) On-chip antennas Architecture & communication protocols Performance evaluation Reliability Error Control Coding Wireline links Wireless links Future Directions Template C Plain-crimson-bright 2

The era of single processor systems is over Why Multi-Core Chips? The need for explosive computational power Scientific applications Weather prediction, Astrophysics Bioinformatics, forensics Language processing Consumer electronics Graphics, Animation Soon be in the Exascale age! The era of single processor systems is over

Moore’s Law: so far so good! The number of transistors on a chip doubles every 18 months Has provided the computational power demanded so far Now poses major challenges Soaring power dissipation due to scaling frequency up Original Moore's Law graph, 1965

Power Density (Watts/cu. m) Power Dissipation Scaling up speed/frequency is impossible 0.1 1 10 100 1,000 10,000 ’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08 Power Density (Watts/cu. m) 4004 8008 8080 8085 8086 286 386 486 Pentium® processors Sun’s Surface Rocket Nozzle Nuclear Reactor Hot Plate Source: Intel

The era of Multi-Core systems Nokia Sparrow To keep up with demands on computational power Scaling of clock frequency is not possible Solution: Increase number of cores - parallelism Intel, AMD dual-core and quad-core CPUs Custom Systems-on-Chip (SoCs) Number of cores need to increase manifold in the next 5-10 years Intel 80 core processor New challenge: interconnection of the cores!

The new interconnection paradigm: Network-on-Chip (NoC) Driven by Massive levels of integration New designs counting 100s of embedded cores Need for platform-based interconnection infrastructure time-to-market

NoC Features and Advantages Packet switched on-chip network Route packets, not wires –Bill Dally, 2000. Dedicated infrastructure for data transport Decoupling of functionality from communication AMBA bus: ARM NoC infrastructure Multiple publications in IEEE ISSCC, 2010 from Intel, IBM, AMD, Renesas Tech. and Sun Microsystems show that multi-core NoC is a reality

4/7/2017 Outline Introduction Multi-core & Network-on-Chip (NoC) paradigm Performance limitations of conventional planar NoCs Alternative interconnect technology Wireless NoC (WiNoC) On-chip antennas Architecture & communication protocols Performance evaluation Reliability Error Control Coding Wireline links Wireless links Future Directions 9 Template C Plain-crimson-bright 9

Limitations of a Traditional NoC Multi-hop wireline communication High Latency and energy dissipation source destination core NoC interface NoC switch 80% of chip power will be from on-chip interconnects in the next 5 years – ITRS, 2007

Novel Interconnect Paradigms for Multicore designs Optical Interconnects Three Dimensional Integration Wireless/RF Interconnects High Bandwidth and Low Energy Dissipation 11

3D NoC Stacking multiple active layers Manufacturability Mismatch between various layers Yield is an issue Temperature concerns Despite power advantages, reduced footprint increases power density Pavlidis et al., “3-D topologies for Networks-on-Chip”, IEEE Transactions on Very Large Scale Integration (TVLSI), 2007.

Photonic NoC High bandwidth photonic links for high payload transfers Challenges: On-going research On-chip integration of photonic components A. Shacham et al., “Photonic Network-on-Chip for Future Generations of Chip Multi-Processors”, IEEE Transactions on Computers, 2008.

NoC with RF Interconnects Use of transmission lines out of package or IC structures like parallel metal wires Challenges: Routing of long transmission lines without eliminating any existing links Causes hotspots at drop-points M. F. Chang et al. “CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect”, Proc. of IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2008.

State-of-the-art in emerging NoCs 3D NoC Photonic NoC NoC with RF-I Design Requirements Multiple layers with active devices Silicon photonic components On-chip waveguide Performance Gains Bandwidth Higher connectivity & less hop count High speed optical devices and links High bandwidth RF waveguide Lower Power Shorter average path length Negligible power dissipation in optical data transport Low power dissipation in RF-I Reliability Vertical Via Failure Crosstalk in photonic waveguides Signal interference in the waveguide Challenges Heat dissipation due to higher power density Integration of on-chip photonic components Precision high frequency oscillators and filters

4/7/2017 Outline Introduction Multi-core & Network-on-Chip (NoC) paradigm Performance limitations of conventional planar NoCs Alternative interconnect technology Wireless NoC (WiNoC) On-chip antennas Architecture & communication protocols Performance evaluation Reliability Error Control Coding Wireline links Wireless links Future Directions 16 Template C Plain-crimson-bright 16

The Wireless Network-on-Chip (WiNoC) Use of on-chip wireless links High bandwidth: 500 Gbps - ~ 1 Tbps Wires: ~ 3 Gbps Latency: True speed-of-light Wires: ~ 400 ps Long distance: ~ 15 mm - 25 mm Wires: ~ 2 - 3 mm No physical interconnect layout is necessary Reduce latency and energy dissipation in communication

Early example of on-chip wireless interconnects First utilized for distribution of clock signal Technology: 0.18 um CMOS Operating frequency: 15 GHz Single Tone Modulation and Channelization was not a concern Floyd et al., IEEE Journal of Solid-State Circuits,2002.

Adopted Technology: Carbon Nanotube (CNT) antennas High B/W, frequency  light (IR, visible, UV) Small wavelength: small antennas less area CNTs as Optical Antennas Directional radiation characteristics Quantitative agreement with conventional radio antenna theory and simulations Laser excitation Kempa, et al., "Carbon Nanotubes as Optical Antennae," Advanced Materials, 2007. Slepyan, et al., "Theory of optical scattering by achiral carbon nanotubes and their potential as optical nanoantennas," Physical Review B, 2006.

How to efficiently distribute the wireless resources? Design Constraints Everything fine? Limited wireless channels Off-chip laser sources On-chip wireless nodes have associated overhead Transceiver Modulator/demodulator antennas How to efficiently distribute the wireless resources?

Hybrid nature of the WiNoC Augment wireline with wireless Not completely wireless Divide the whole NoC into multiple subnets Communication within the subnets is still through wires Utilize wireless links for inter-subnet data exchange Each subnet will have a hub Equipped with Wireless Base Station (WB) Subnet architectures may vary and even be heterogeneous on the same chip

Network Design Principles Topology Establish connectivity among the subnets through hubs Reduce multi-hop communication using the wireless channels Near constant bandwidth over all range of communication Can be used as long-distance shortcuts Adopt SMALL-WORLD network topology Communication mechanism How to send bits through the CNT antennas Minimize the WB overhead Simple yet efficient physical layer

Connecting the Hubs Small-World graphs: The Watts-Strogatz Model Often found in nature Scales well: low average distance regular lattice L: Hi C: Hi random graph L: Lo C: Lo Small-world L: Lo C: Hi Few high speed shortcuts: Wireless Local, shorter links: Wireline

Proposed Hybrid, Hierarchical WiNoC Architecture Mesh-based wireline subnets Each subnet has a hub Interconnected with neighboring hubs in a ring topology Some hubs have WBs Providing wireless shortcuts Creating small-world topology in the upper level

How to establish wireless links? Simulated Annealing Shortcuts, but where? Optimization metric Distance, frequency of communication Convergence is faster than exhaustive search Scalable technique Stable convergence for several cooling profiles

Network Design Principles Topology Establish connectivity among the subnets through hubs Reduce multi-hop communication using the wireless channels Near constant bandwidth over all range of communication Can be used as long-distance shortcuts Adopt SMALL-WORLD network topology Communication mechanism How to send bits through the CNT antennas Minimize the WB overhead Simple yet efficient physical layer 26

Communication mechanisms with CNT antennas Multiband laser sources to excite the antennas Frequency Division Multiplexing (FDM) Different frequency channels can be assigned to pairs of communicating subnets Antenna elements tuned to different frequencies No complex MAC required Electro-Optic Conversions Mach-Zehnder Modulators (MZM) Perform OOK on light carrier Supported B/W of 10Gbps/channel An ultra compact 10 Gbps silicon modulator Green et. al., “Ultra-compact, low RF power, 10Gb/s silicon Mach-Zehnder modulator,” Optics Express, 2007

Adopted channelization scheme 32-bit flit width 24 distinct frequency channels Total wireless B/W of 240 Gbps m wireless links 1-24 links 24/m distinct frequency channels per link Combination of FDM and TDM.

Performance Evaluation Comparison with Flat wireline mesh Scaling methods with size Comparisons with other emerging NoCs Overheads

Compared with flat wireline mesh System size: 256 cores Throughput Packet Energy System Size Flat Mesh (nJ) WiNoC (nJ) ratio 128 1319 22.57 58 256 2936 24.02 122 512 4992 37.48 133 Orders of magnitude less ! Gets better with size Ganguly et al., “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), 2010.

Establishment of scaling trend Packet Energy dissipation Varying subnet size and number Varying number of wireless links Scales better with increase in number of subnets

Comparative Performance Evaluation Case study:128 cores Achievable network bandwidth Packet Energy dissipation WiNoC performs best

About 10-20% area overhead depending on the system size Overheads Area Overhead Wiring overheads Additional links Core-hub Inter-hub About 10-20% area overhead depending on the system size

Summary of WiNoC Performance Up to 2 orders of magnitude less energy dissipation Much higher bandwidth compared to wireline NoCs of same size Better performance than all other emerging NoC paradigms Reasonable real estate overheads

4/7/2017 Outline Introduction Multi-core & Network-on-Chip (NoC) paradigm Performance limitations of conventional planar NoCs Alternative interconnect technology Wireless NoC (WiNoC) On-chip antennas Architecture & communication protocols Performance evaluation Reliability Error Control Coding Wireline links Wireless links Future Directions 35 Template C Plain-crimson-bright 35

Reliability and Signal Integrity According to ITRS signal integrity will become a major issue in future technologies Shrinking geometries: less charge/information Increased probability of transient events like: Crosstalk Ground Bounce Alpha particle hits WiNoCs Use of inherently defect prone CNT technology Error Control Coding is a solution 36

ECC: Wireline links Joint Codes Proposed codes Optimization Crosstalk Avoidance Codes Error Correction Codes Proposed codes CADEC: double error JTEC: triple error JTEC-SQED: quadruple error Optimization Hsiao SEC-DED code

Joint Codes Voltage Swing reduction Asymptotic reduction Lower noise margins Asymptotic reduction Increasing error correction capability Disadvantageous beyond 4 errors

Energy Dissipation Characteristics ECCs in subnet links 64 core wireline NoC 33% 47% Ganguly et al., “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) 2009. 39

ECC: Wireless links Each CNT antenna element responsible for multiple bit transmission Burst Errors Multi-bit error Multi-path interference Packaging surfaces 40

SNR & BER Single transmitter position Reception across die area Non-coherent OOK modem 0.001

Structure of the product code encoder Using simple ECCs on both spatial and time axes Hamming codes Hamming-Product Code (H-PC) Structure of the product code encoder

Results Increase reliability Keep energy dissipation low Low latency

4/7/2017 Outline Introduction Multi-core & Network-on-Chip (NoC) paradigm Performance limitations of conventional planar NoCs Alternative interconnect technology Wireless NoC (WiNoC) On-chip antennas Architecture & communication protocols Performance evaluation Reliability Error Control Coding Wireline links Wireless links Future Directions 44 Template C Plain-crimson-bright 44

Future Directions Wireless NoCs with millimeter-wave Interconnects Extension of the ECC schemes Unified design framework with alternative interconnect technologies Complex Networks

Alternative Antennas CNTs still have manufacturing issues Metal Zig-Zag antennas Bandwidth: ~ tens of GHz

Another alternative antenna Electrolumiscence in CNTs No separate modulator/demodulators required Much less overhead Range of communication needs to be investigated Can be used for short range wireless interconnects Nojeh et. al., "Reliability of wireless on-chip interconnects based on carbon nanotube antennas," International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008.

Extension of ECC schemes Use of multiple error correction codes Space Time Both Correct multiple bursts in either direction BCH codes RS codes Study performance Performance-overhead trade-offs

Unified Framework All alternative interconnect technologies Network topologies with all the possible interconnects Determine each one’s spot in the design space Look across varying granularity for optimization Nodes: subnets to even devices Develop CAD methodologies for novel interconnects Can an optimal solution for N cores readily be scaled up to 10N or 1000N cores? If not, what is the difference and what are the design rules as the system scales up? Super low-power interconnects Sustainability of computing: Scalability Green computing paradigms

Fault Tolerance: Complex Networks Small-World/Exponential graphs Nodes with similar degrees Resilient to targeted attacks Scale-free graphs Few high-degree nodes Resilient to random failures R. Albert, H. Jeong and A. Barabási, “Error and Attack Tolerance of Complex Networks”, Nature, Vol. 406, July 2000, pp. 378-382.

Conclusions NoC is a reality Alternative interconnect technology Limitations: performance & energy Alternative interconnect technology High bandwidth, low power Long distance shortcuts Adopt nature-inspired topologies Optimize network Increase reliability ECC Complex Network theory

Journal Publications Amlan Ganguly, Kevin Chang, Sujay Deb, Partha Pande, Benjamin Belzer, Christof Teuscher, “Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems”, IEEE Transactions on Computers (TC), June, 2010, accepted for publication. Amlan Ganguly, Partha Pande, Benjamin Belzer, “Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NoC Interconnects”, IEEE Transactions on VLSI (TVLSI) Vol. 17, No.11, November 2009, pp. 1626-1639. Amlan Ganguly, Partha Pande, Benjamin Belzer, Cristian Grecu, "Design of Low power & Reliable Networks on Chip through joint Crosstalk Avoidance and Multiple Error Correction Coding", Journal of Electronic Testing: Theory and Applications (JETTA), Special Issue on Defect and Fault Tolerance, June 2008, pp. 67-81. Partha Pande, Amlan Ganguly, Haibo Zhu, Cristian Grecu, “Energy Reduction through Crosstalk Avoidance Coding in Networks on Chip", Journal of System Architecture (JSA), Vol. 54/ 3-4, March-April 2008, pp.441-451.

Conference Publications/Book Chapters Partha Pratim Pande, Cristian Grecu, Amlan Ganguly, Andre Ivanov, and Resve Saleh, “Test and Fault Tolerance of NoC Infrastructures”, In Networks-on-Chips: Theory and Practice, Fayez Gebali, Haytham Elmiligi, and M.Watheq El-Kharashi (eds.), Taylor & Francis Group LLC - CRC Press. Sujay Deb, Kevin Chang, Amlan Ganguly and Partha Pande, “Comparative Performance Evaluation of Wireless and Optical NoC Architectures”, Proceedings of IEEE International SOC Conference (SOCC), 27th-29th September 2010. Sujay Deb, Amlan Ganguly, Kevin Chang, Benjamin Belzer, Deuk Heo, “Enhancing Performance of Network-on-Chip Architectures with Millimeter-Wave Wireless Interconnects”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2010. Partha Pande, Amlan Ganguly, Kevin Chang, Christof Teuscher, “Hybrid Wireless Network-on-Chip: A New Paradigm in Multi-Core Design”, invited paper, Second International Workshop on Network-on-Chip Architectures (NoCArc), December 12, 2009. Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer and Alireza Nojeh, "Performance Evaluation of Wireless Networks on Chip Architectures", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), 16th-18th March 2009. Partha Pande, Amlan Ganguly, Benjamin Belzer, Alireza Nojeh, Andre Ivanov, “Novel Interconnect Infrastructures for Massive Multicore Chips”, Proceedings of IEEE Symposium on Circuits and Systems (ISCAS) , May, 2008, pp. 2777 - 2780.

Conference Publications contd. A. Nojeh, P. Pande, A. Ganguly, S. Sheikhaei, B. Belzer and A. Ivanov, "Reliability of wireless on-chip interconnects based on carbon nanotube antennas," Proceedings of IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW) June 2008, pp. 1-6. Amlan Ganguly, Partha Pande, Benjamin Belzer, Cristian Grecu, “Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding”, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2007, May, 2007, pp. 317 - 324. Partha Pande, Amlan Ganguly, Brett Feero, Cristian Grecu, “Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics”, Proceedings of IEEE International ON-line Test Symposium (IOLTS), July, 2007, pp. 161-166. Partha Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu, "Design of Low Lower & Reliable Networks on Chip through Joint Crosstalk Avoidance and Forward Error Correction Coding", Proceedings of IEEE Defect and Fault Tolerance in VLSI Systems (DFT), 2006, pp. 466 – 476. Partha Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu, “Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm", Proceedings of IEEE EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD) 2006, pp. 689 – 695. Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu, "Crosstalk-aware Energy Reduction in NoC Communication Fabrics", Proceedings of IEEE International SOC Conference (SOCC), 2006, pp. 225 – 228.

Acknowledgements Advisor Collaborators Colleagues in my Lab Family Dr. Partha Pande, WSU through NSF CAREER Grant Collaborators Dr. Benjamin Belzer, WSU Dr. Alireza Nojeh, UBC Dr. Christof Teuscher, PSU Dr. Deuk Heo, WSU Intel, CRL, OR Colleagues in my Lab Mr. Kevin Chang, WSU Mr. Sujay Deb, WSU Family Parents Rini

Thank you