1CONFIDENTIAL©2005-2009 GHz Circuits, Inc. TOPS Accurate TOp Level PLL Simulator April 13, 2007.

Slides:



Advertisements
Similar presentations
Improved Howland Current Pump Stability
Advertisements

ITRS Roadmap Design + System Drivers Makuhari, December 2007 Worldwide Design ITWG Good morning. Here we present the work that the ITRS Design TWG has.
D. Wei, Y. Huang, B. Garlepp and J. Hein
The World Leader in High-Performance Signal Processing Solutions 1.ADCs - Ping-Pong Architectures 2.ADCs – Driving Them 3.DACs – Sinc Compensation 4.DACs.
Balanced Device Characterization. Page 2 Outline Characteristics of Differential Topologies Measurement Alternatives Unbalanced and Balanced Performance.
0 - 0.
DIVIDING INTEGERS 1. IF THE SIGNS ARE THE SAME THE ANSWER IS POSITIVE 2. IF THE SIGNS ARE DIFFERENT THE ANSWER IS NEGATIVE.
Addition Facts
Dependability analysis and evolutionary design optimisation with HiP-HOPS Dr Yiannis Papadopoulos Department of Computer Science University of Hull, U.K.
Filters and Enveloping - A Practical Discussion -
Reading Assignment: Chapter 8 in Electric Circuits, 9th Ed. by Nilsson
ECE 495: Integrated System Design I
A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.
Charge Pump PLL.
Introduction to Electronic Circuit Design
1 © 2011 The MathWorks, Inc. Designing Control Systems for Wind Turbines Steve Miller Technical Marketing, Physical Modeling MathWorks Root LocusBode Plot.
Build to kick kick to win. Shooting skills 2 Outline Shooting mechanism System description Actuator design Lob shots Identification Calibration Towards.
1 1 Mechanical Design and Production Dept, Faculty of Engineering, Zagazig University, Egypt. Mechanical Design and Production Dept, Faculty of Engineering,
1 General-Purpose Languages, High-Level Synthesis John Sanguinetti High-Level Modeling.
…We have a large reservoir of engineers (and scientists) with a vast background of engineering know-how. They need to learn statistical methods that can.
EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department.
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
S Transmission Methods in Telecommunication Systems (5 cr)
The need for AMS assertions Verify the analog/digital interfaces at block and SoC levels –Check properties involving voltages and currents –Check complex.
1CONFIDENTIAL© GHz Circuits, Inc. TOPS Accurate TOp Level PLL Simulator April 14, 2007.
Case Study: Implementation Aspects of a GFDM-based Prototype for 5G Cellular Communications Ivan Simões Gaspar With the Vodafone Chair (Prof. Fettweis)
Addition 1’s to 20.
QR026 High Sensitivity VME Tuner Performance Data
UH page: 1 / Sept nd Intl. AES Conference “DSP for Loudspeakers” Hillerod, Denmark Application of Linear-Phase Digital Crossover.
EE105 Fall 2007Lecture 13, Slide 1Prof. Liu, UC Berkeley Lecture 13 OUTLINE Cascode Stage: final comments Frequency Response – General considerations –
Math Review with Matlab:
Slide 1 Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed- Signal Circuits by Reusing Early-Stage Data Fa Wang*, Wangyang Zhang*,
Analog-to-Digital Converter (ADC) And
Chapter 2Test Specification Process. n Device Specification Sheet – Purpose n Design Specification – Determine functionality of design n Test List Generation.
Worst Case Analysis Using Analog Workbench by Andrew G. Bell ITT Industries.
5/4/2006BAE Analog to Digital (A/D) Conversion An overview of A/D techniques.
How to Accelerate the Analog Design Verification Flow Itai Yarom Senior Verification Expert Synopsys.
MATLAB Applications By: Ramy Yousry.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
Polar Loop Transmitter T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, I. Gheorghe.
Crystal Oscillator Negative Resistance Measurement System
1 High Speed Fully Integrated On-Chip DC/DC Power Converter By Prabal Upadhyaya Sponsor: National Aeronautics and Space Administration.
EE311: Junior EE Lab Phase Locked Loop J. Carroll 9/3/02.
Phase Locked Loop Design Matt Knoll Engineering 315.
Brief Introduction of High-Speed Circuits for Optical Communication Systems Zheng Wang Instructor: Dr. Liu.
GUIDED BY: Prof. DEBASIS BEHERA
1 Phase-Locked Loop. 2 Phase-Locked Loop in RF Receiver BPF1BPF2LNA LO MixerBPF3IF Amp Demodulator Antenna RF front end PD Loop Filter 1/N Ref. VCO Phase-
Technion – Israel Institute of Technology Department of Electrical Engineering Winter 2009 Instructor Amit Berman Students Evgeny Hahamovich Yaakov Aharon.
CHAPTER 15 Special ICs. Objectives Describe and Analyze: Common Mode vs. Differential Instrumentation Amps Optoisolators VCOs & PLLs Other Special ICs.
A New Method For Developing IBIS-AMI Models
Design of Front-End Low-Noise and Radiation Tolerant Readout Systems José Pedro Cardoso.
TELECOMMUNICATIONS Dr. Hugh Blanton ENTC 4307/ENTC 5307.
1 A Frequency Synthesizer Using Two Different Delay Feedbacks 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授 Circuits and Systems, ISCAS IEEE International Symposium.
LC Voltage Control Oscillator AAC
Oct 13, 2005CS477: Analog and Digital Communications1 PLL and Noise in Analog Systems Analog and Digital Communications Autumn
111 Communications Fall 2008 NCTU EE Tzu-Hsien Sang.
Delay-based Spread Spectrum Clock Generator Subramaniam Venkatraman Matthew Leslie University of California, Berkeley EE 241 Final Presentation May 9 th.
Mackenzie Cook Mohamed Khelifi Jonathon Lee Meshegna Shumye Supervisors: John W.M. Rogers, Calvin Plett 1.
Custom ICs for Radiation Detection & Imaging
PLL Sub System4 PLL Loop Filter parameters: Loop Type and Order
Created by Tim Green, Art Kay Presented by Peggy Liska
Overview Modern chip designs have multiple IP components with different process, voltage, temperature sensitivities Optimizing mix to different customer.
PSCAD models.
B.Sc. Thesis by Çağrı Gürleyük
Time Domain and Frequency Domain Analysis
Analogue Electronic 2 EMT 212
DESIGN AND SIMULATION OF A PHASE LOCKED LOOP FOR HIGH SPEED SERDES
Real Number Modeling Enables Fast, Accurate Functional Verification
TLK10xxx High Speed SerDes Overview
Electromagnetic Crosstalk Analysis and Sign-off For Advanced Node SoCs
Presentation transcript:

1CONFIDENTIAL© GHz Circuits, Inc. TOPS Accurate TOp Level PLL Simulator April 13, 2007

2CONFIDENTIAL© GHz Circuits, Inc. Contents Background & Motivation Traditional Solutions Proposed Solution TOPS Overview User Interface Example Summary Benefits Extensions Market Segments Contact info

3CONFIDENTIAL© GHz Circuits, Inc. Background PLLs are complicated 3 rd or higher order, non-linear, discrete-time, time-varying 1 feedback control systems Meeting tight standards mandated goals and even tighter jitter specifications requires extensive expertise, time & compute resources Need answers early in design process for tradeoffs and need exhaustive simulations later on for tolerance/margin/yield analysis There is necessity for a tool which provides circuit-simulator accurate measurements with behavioral-simulator speeds. 1.PLL loop parameters will change with time domain variations in supply (noise) for example, hence these parameters can be considered time-dependent. Also, in some applications like Fractional N synthesizers, the divider counts could be varied in time making the PLL loop parameters time-dependent.

4CONFIDENTIAL© GHz Circuits, Inc. Standards Mandates PCI Express –2MHz < 3dB_BW < 22MHz –0.54 <  –Peak Jitter Transfer < 3dB Sonet (OC xxx) –f c < Jitter Transfer Rolloff –Peak Jitter Transfer < 0.1 dB DVI/HDMI –Jitter transfer amplitude shall not deviate from ideal (single pole 4MHz roll off) by ± 0.2dB from DC to 10MHz Communications: Jitter performance –Advances in signaling speeds continuously tightens jitter specifications (TX) and losens jitter tolerances (RX)

5CONFIDENTIAL© GHz Circuits, Inc. Design to Standards Compliance Traditional Methods Rely on “Classical” theory/formulae which erroneously force fits the design to possibly 2 nd order or continuous time domain Rely on in-house developed behavioral code (such as Matlab etc) Run very time consuming transient simulations After running out of time, Rely on “thumb-rules” and “gut-calls” In summary, either “shoot in the dark and hope to hit the target” or expend incredible amounts time and compute resources

6CONFIDENTIAL© GHz Circuits, Inc. Solution TOPS: circuit-simulator accurate behavioral simulator with 3- 4 orders of magnitude improvement in speed. Use TOPS in the architecture phase to determine PLL parameters to meet specifications Implement circuits per design parameters Use Circuit Simulator to verify functionality and a few step/impulse response closed loop simulations just to verify TOPS accuracy Use TOPS with extracted non-linear sub-circuit characteristics for exhaustive tolerance/margin/yield analysis Use TOPS with time-varying models and noise-scenarios for exhaustive jitter analysis Get the confidence that circuit will meet specifications pre- tapeout and simultaneously reap the benefits of time-savings to tapeout.

7CONFIDENTIAL© GHz Circuits, Inc. TOp level PLL Simulator Overview A Top Level PLL simulator –ACCURACY: Within a few % accuracy of circuit simulator, with 3-4 orders of magnitude speed improvement –MODELING: Ability model sub-blocks as linear, non- linear or time-varying circuit extracts –PARAMETER EXTRACTION: Push button extraction of critical closed loop parameters (ω 3dB, Jitter Peak, ζ, ω n, Phase-margin) –JITTER ANALYSIS: Comprehensive jitter analysis based on user defined noise vectors

8CONFIDENTIAL© GHz Circuits, Inc. TOPS: User Interface (i)

9CONFIDENTIAL© GHz Circuits, Inc. TOPS: User Interface (ii)

10CONFIDENTIAL© GHz Circuits, Inc. Case Study: Impulse Response Comparison with Cadence Spectre Impulse response for a fully differential 6.4GHz LC oscillator is simulated in Circuit Simulator (Cadence Spectre) & TOPS PLL is allowed to lock in Circuit simulator and a Reference Clock phase step of 200ps is applied at 2uS PLL is modeled as a linear system in TOPS with circuit extracted parameters. Next page shows superposition of the phase tracking error & instantaneous VCO frequency for both Circuit Simulator & TOPS Output is viewed with Synopsys AWAVES waveform viewer

11CONFIDENTIAL© GHz Circuits, Inc. Case Study: Impulse Response Simulation Results Overlay Spectre TOPS Spectre TOPS

12CONFIDENTIAL© GHz Circuits, Inc. Case Study: Impulse Response Summary of Results ACCURACY: The superimposed plots show TOPS step response very closely matches Circuit Simulator phase step response, even using linearized models for TOPS simulation. Zero Crossing (ω n indicator)-3.4% Peak Undershoot (ζ indicator)2.2% Difference in integrated error is within a few % and difference in instantaneous VCO frequency is negligible Circuit Simulator shows numerical noise in instantaneous frequency plot which is dependent on timestep resolution. Circuit Simulator run time ~ 10 h TOPS run time ~ 1.2 s

13CONFIDENTIAL© GHz Circuits, Inc. Summary Accurate to Circuit Simulator within a few % Speed improvement of 3-4 orders of magnitude Intuitive & User friendly GUI Push-button extraction of critical design-to parameters

14CONFIDENTIAL© GHz Circuits, Inc. Benefits Accuracy and significant simulation time savings enable Exhaustive what-if analysis & optimization at architecture level Exhaustive tolerance/margin/yield analysis at post circuit design/layout level Exhaustive Jitter analysis for user specified noise scenarios Formal analog-verification Ability to run bench test measurements prior to tapeout

15CONFIDENTIAL© GHz Circuits, Inc. Cost Benefits Reduction in simulation/verification time and time to tape-out Reduction in simulator licenses Reduction in Hardware to run simulators Reduction in Silicon spins

16CONFIDENTIAL© GHz Circuits, Inc. Extensions to different Market Segments The engine can be extended to benefit other continuous-time systems with discrete-time control –SERDES (CDR) –RF (Fractional-N synthesizer)

17CONFIDENTIAL© GHz Circuits, Inc. Verticals Analog/Mixed-Signal/SOC –Chip Design Companies –IP design Companies –IP purchaser Companies –System Companies

18CONFIDENTIAL© GHz Circuits, Inc. Known Competition Agilent Eagleware Genesys –Agilent purchased Eagleware for a few million –This however is does not have circuit-accurate modeling of sub-blocks –We believe TOPS is significantly faster –This does not have post processing engines for optimization/formal- verification etc. Freeware –There are a few freely available software but quality, support, verification w.r.t. industrial designs/silicon is unproven WaveCrest –This is not exactly competition as Wavecrest has tools to measure similar results post-silicon. –One of our goals is to provide WaveCrest type measurements pre- silicon

19CONFIDENTIAL© GHz Circuits, Inc. Contact Info Nandu Bhagwan GHz Circuits, Inc 1030 E. El Camino Real, PMB 232 Sunnyvale, CA \(408)\7/8/1\0/9/8/9/ Nandu_at_ghzcircuits_dot_com