# Introduction to Electronic Circuit Design

## Presentation on theme: "Introduction to Electronic Circuit Design"— Presentation transcript:

Introduction to Electronic Circuit Design
Richard R. Spencer Mohammed S. Ghausi Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 1

Figure 11-1 Ideal filter transfer function: (a) low-pass, (b) high-pass, (c) bandpass, (d) bandstop (or notch), and (e) allpass. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 2

Figure 11-2 (a) The Bode magnitude plot and (b) phas plot for an ideal low-pass filter with cutoff frequency wc = 1 rad/s and delay tp = 1 s. (c) The impulse response of the filter and (d) the step response. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 3

Figure 11-3 The pole locations of a Butterworth transfer function with N = 4. The poles are equally spaced around the left half of a unit circuit and are symmetric about the real axis. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 4

Figure 11-4 The Butterworth magnitude responses for N = 1, 2, 3, and 4.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 5

Figure 11-5 Specifications for a low-pass filter
Figure 11-5 Specifications for a low-pass filter. A transfer function that meets these specifications is also shown. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 6

Figure 11-8 Magnitude and phase of the standard second-order transfer function for Q = 1, 0.707, and 0.3. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 7

Figure 11-9 The Chebyshev magnitude responses for N = 3 and 4 with e = (a 1-dB ripple). The frequency is normalized to the edge of the ripple band, instead of the cutoff frequency. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 8

Figure 11-11 (a) Ideal bandpass characteristics
Figure (a) Ideal bandpass characteristics. (b) Practical bandpass characteristics. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 9

Figure A11-1 (a) A message signal and (b) the resulting amplitude-modulated signal.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 10

Figure 11-16 (a) Low-pass pole location
Figure (a) Low-pass pole location. (b) Corresponding bandpass pole locations found using the narrowband low-pass-to-bandpass transformation. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 11

Figure 11-18 The Butterworth bandpass magnitude response.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 12

Figure 11-19 A feedback amplifier with a frequency-dependent feedback network.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 13

Figure 11-22 An RC integrator.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 14

Figure 11-23 A switched-capacitor integrator.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 15

Figure 11-24 (a) The switched-capacitor integrator
Figure (a) The switched-capacitor integrator. (b) The nonoverlapping clocks. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 16

Figure 11-29 A transversal, or tapped-delay line, FIR filter.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 17

Figure Two single-stage single-tuned amplifiers: (a) a stage with voltage and current gain (common merge) and (b) a stage with voltage gain (common control). Figure The small-signal AC equivalent circuit for the amplifier in Figure 11-35(a). Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 18

Figure 11-37 Universal resonance curve for a single-tuned amplifier.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 19

Figure (a) Pole-zero plot of a stagger-tuned maximally flat magnitude design using two single-tuned stages. (b) Magnitude responses for the individual tuned circuits and the overall stagger-tuned design. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 20

Figure 11-48 The block diagram of a basic PLL.
Figure The VCO control voltage and loop input voltage for a PLL when tracking changes in the input frequency. Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 21

Figure 11-50 A Laplace-domain block diagram for the PLL when locked.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc Chapter 11, slide 22