TPC / PHOS / HLT Readout Electronics overview Annual Evaluation Meeting for CERN-related Research in Norway November, 2004 University of Oslo Kjetil Ullaland

TPC & PHOS RCU + HLT Readout Electronics and Firmware Team Ruprecht-Karls Universität Heidelberg, Germany V. Lindenstruth D. Gottschalk M. Stockmaier V. Kiworra T. Alt T. Krawutschke ZTT Worms, Germany S. Bablock C. Kofler CERN L. Musa R. Campagnolo C. González Gutiérrez B. Leitao Mota University of Bergen D.Röhrich K.Ullaland B. Pommersche J. Alme (new phD-stipend, 2004) M. Richter (phD-stipend, 2004) T. Alt (Marie Currie stipend, ) G. Grastveit (MsC, 2003) K. Aurbakken (MsC-student) O. Torheim (MSc-student) University of Oslo B. Skaali S. Solli (MSc-student) P. T. Hille (MSc-student) Bergen University College H. Helstrup J. Lien (handed in phD thesis, 2004) K. Røed (MSc 2004, phD-stipend, 2004) L. E. Danielsen (BSc, 2003) M. S. Myhre (BSc, 2003) RCU design, prototyping and test results (TPC & PHOS) Radiation tolerance for electronics HLT overview Phos test beam results

ConfigFPGA SIU Mezzanine Board FEB AFEB B Power Triggers & Clocks DCS Mezzanine Board DAQ System Detector Control System HLT System Readout Control Unit Trigger System

RCU – FEC Assembly

510 cm E E cm The ALICE Time Projection Chamber pads x 1000 samples = 712 Mbytes / event –2 scenarios: Pb – Pb 200 Hz)  Gbytes / s p – p 1 KHz)  712 Gbytes / s –Data compression (zero suppression) in FEE

RCU Ethernet ( 1 MB/s ) Detector Data Link ( 200 MB / s ) COUNTING ROOM ALTRO bus ( 200 MB / s ) Local Slow- Control (I 2 C-serial link) ON DETECTOR FEC 128 ch DCS int. (Ethernet) SIU int. (DDL-SIU) Trigger int. (TTC-RX) FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch PASA – ADC – DIG. DETECTOR TTC optical Link (Clock, L1 and L2 ) Overall TPC: 4356 Front End Card 216 Readout Control Unit ALTRO Bus Interface Slow Control Interface Data assembler Branch A Branch B RORC (PCI) DCS TTC

ALICE Photon Spectrometer (PHOS) 5x3584 XTALs 5x112 Front End Cards 5x8 Readout Control Units

RCU Ethernet ( 1 MB/s ) Detector Data Link ( 200 MB / s ) COUNTING ROOM ALTRO bus ( 200 MB / s ) Local Slow- Control (I 2 C-serial link) ON DETECTOR FEC 32 ch DCS int. (Ethernet) SIU int. (DDL-SIU) Trigger int. (TTC-RX) FEC 32 ch FEC 32 ch FEC 32 ch PASA – ADC – DIG. DETECTOR TTC optical Link (Clock, L1 and L2 ) Overall PHOS: 5x3584 XTALs 5x112 Front End Cards 5x8 Readout Control Units ALTRO Bus Interface Slow Control Interface Data assembler Branch A Branch B RORC (PCI) DCS TTC Debugging Bus (USB-serial link) Trigger card 28 FECs Trigger card 28 FECs

Local Pattern Recognition High Level Trigger ✔ Commercial off-the-shelf PCs ● ~ 300 PCs equipped with FPGA Co-processor cards with Firmware Algorithms ● ~ compute nodes ✔ Fault-tolerant cluster management ✔ Publisher-Subscriber Interface

HLT data input / output

HLT FEP Architecture Detector Data Link Data pointer List Push readout Pointers FPGA PCI 66/64 PCI Host memory PCI Hostbridge small Derandom. Evt. Buffer CPU iCache dCache CPU iCache dCache CPU iCache dCache CPU iCache dCache NetworkInterface 200 MB/s max. per design ≈ 90 MB/s typical

RCU Motherboard - Bottom view ALTERA APEX20KE GTL Transceivers Backplane readout connectors

RCU Motherboard - Top view DCS interface DIMM connector Power regulators SIU PMC connectors TEST and DEBUG connectors

TTC and DCS mezzanine card Tasks: –Configuration –RCU –FEC –monitoring / controlling the FEE –configuration/readout of the TTCrx –distributing the L1 and L2 ALTERA Excalibur: –FPGA EP20K100 –ARM922T hardwired processor running Linux TTCrx chip (custom) Ethernet bridge

DDL - SIU mezzanine card