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ESE 566: Hardware/Software Co-Design of Embedded Systems Fall 2005 Instructor: Dr. Alex Doboli. Paper discussed in class: S. Hauck, T. Fry, M. Hosler, J. Kao, “The Chimaera Reconfigurable Functional Unit”, IEEE Transactions on VLSI Systems, Vol. 12, No. 2, February 2004, pp. 206-217.

Brief description of the paper content Briefly, what is the paper discussing? What is different from other reconfiguration approaches, like Pleiades or Morphosys? What limitations did the authors identify for FPGA systems? What limitations is this paper addressing?

Chimaera Execution Model What is the reason for using reconfigurable logic? Explain the Chimaera execution model. What is the granularity of reconfiguration? How is reconfiguration achieved?

Chimaera Execution Model How are RFU instructions executed? How is reconfiguration time reduced?

Chimaera Execution Model Explain the handling of data registers. Explain the speculative execution concept. What is difficult in this speculative execution model? What are its limitations?

Chimaera Architecture Discuss Figure 1.

Chimaera Architecture Discuss Figure 2. How is reconfigurable logic organized? How is data accessed? What are the inputs? What are the outputs? Do you see any problems between the execution model and the nature of the inputs? Describe a procedure for evaluating the quality of the reconfigurable routing. Selecting the basic reconfigurable block is very important. Do you see a systematic procedure for this selection?

Chimaera Architecture Discuss Figure 3. Discuss the other specific elements of the Chimaera architecture.

Summary Summarize the concepts. In conclusion, where is the speedup actually coming from?