A 90nm RF CMOS technology supported by device modelling and circuit demonstrators J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten 1, S. Jenei, S. Thijs, A.J. Scholten 2, P. Wambacq 1, I. Debusschere, S. Decoutere IMEC Leuven, Belgium 1 Also with the Vrije Universiteit Brussel, Belgium 2 Philips Research Eindhoven, Netherlands

Outline of the presentation Introduction Technology overview Active device description and modelling Passive devices description and modelling Circuit demonstrators results Conclusions

Introduction CMOS technology traditionally used for digital applications 90nm ~ 3.6GHz 130nm ~ 1.5GHz 180nm ~ 1GHz Aggressive Down-scaling for High-performance microprocessors Lg Lg fT fT 150GHz for a 90nm CMOS process * Purely CMOS RF- Mixed-signal System-on-Chip * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004 European IST IMPACT project Pushing CMOS technology for its use in products operating well into the radio frequencies (5-20 GHz)

90nm CMOS technology* Active Device 20 -cm P type Si substrate 1.5nm EOT nitrided oxide dielectric 5nm EOT Dual Gate Oxide device 150nm poly gate stack Cobalt silicide 5 Metal layer Cu back end of line * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004

Passive Devices Cu back end of line High-Q inductors High-Q MIM capacitors Junction varactors MOS-like accumulation-depletion varactors 90nm RF CMOS technology *S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001 **G.J.Carchon et al., IEEE Trans. on Microwave Theory and Techniques, April 2004

CMOS Transistor L physical ~ 70nm Saturation V t ~ 0.3V I on, NMOS =720 A/ m, I on, PMOS =320 A/ m I off, NMOS = I off, PMOS =1.5nA/ m ~15ps inverter delay Digital key performances NMOS

CMOS Transistor Analogue/RF key performances Moderate inversion Up to 5GHz applications. Low power consumption. Strong inversion Up to 20GHz applications. Higher power consumption. Design specification: f max and f T > 5-10 times f application ** J. Ramos et al. ESSDERC, September 2004 * W. Jeamsaksiri et al. Symposium on VLSI Technology, June, 2004

CMOS Transistor modelling MOS Model requirements? Intrinsic model at any operation regime (I d –V g, Chargers) First and higher order derivatives of I d (g m /I d, g m /g ds,Distortion) Current noise (1/f, Thermal and Induced Gate noise) RF model (Impedance levels, current and power gains) Non Quasi static effects (High frequencies, large devices) Scalability (Freedom of design)

CMOS Transistor modelling MOS Model 11 – The choice All requirements fulfilled Moderate inversion Distortion Noise RF extension NQS Scalability RGRG G D S B SUB R jun,S R jun,D R bulk MM11 R sub C well Substrate Network Gate Resistance Intrinsic Device Juncap * R. van Langevelde et al. NanoTech MSM, pag , April 2002

CMOS Transistor modelling MOS Model 11 – DC modelling g m /I d and g m /g ds S-parameters Low frequency points Distortion DC operation point Moderate inversion L design =100nm W design =10 m *Courtesy of Philips Research Laboratories

CMOS Transistor modelling MOS Model 11 – Analogue modelling Gate capacitance (accumulation to inversion, poly-depletion) Overlap capacitances (Bias dependent) Junction capacitance (STI-edge, gate-edge and bottom effects) *Courtesy of Philips Research Laboratories

CMOS Transistor modelling NQS MOS Model 11 – S-Parameters fTfT 5-20 GHz range covered

Passive Devices Passive device processed on standard 5LM Cu/Oxide BEOL. Provide circuit designers with a complete set of devices. In-house RF SPICE models. Alternative add-on solution for High-Q inductors

Metal Insulator Metal Capacitor MIM Technology Specific capacitance of 1.1fF/ m 2 Embedded in Cu BEOL (M2- M3) TaN plates ( /square) 35nm Silicon Oxide dielectric *S. Jenei et al. Topical Meeting on Silicon Monolithic Integrated Circuits, 2001

Metal Insulator Metal Capacitor MIM In-house RF Model Pass-through equivalent circuit Coupling to substrate Q 11 =-Im(1/y 11 )/Re(1/y 11 ) Top plate grounded Q 22 =-Im(1/y 22 )/Re(1/y 22 ) Bottom plate grounded 429fF (Optimized layout) 443fF Lines Models Symbols Measurement data Q 11 Q fF MIM Capacitor

Variable Capacitors - Varactors Varactor Technology N+/Pwell and P+/Nwell Junction varactors MOS-like accumulation-depletion varactor N+ oxide Poly - silicon N+ Nwell 7.0E E E E E E E V bias (V) C (F) N+/Pwell P+/Nwell

Variable Capacitors - Varactors Junction varactor In-house RF Model Linear passive components Spice diode models Frequency and bias dependent Pass-through equivalent circuit

Variable Capacitors - Varactors MOS-like varactor In-house RF Model Pass-through equivalent circuit Linear passive components Frequency and bias dependent

BEOL High Q Inductors 5 Level of Metal Cu/Oxide BEOL Inner Outer Conventional CMOS Cu/oxide BEOL High sheet resistance (35m /square) Lossy substrate (20 -cm P type) Spiral Shunted M4 & M5 Underpass Shunted M2 & M3 Patterned Poly or M1 shield GSG GSG IMD4 IMD3 IMD2 IMD1 PMD *S. Jenei et al. Electron Device Letters, April 2002

BEOL High Q Inductors BEOL Inductors In-house RF Model Double lumped equivalent circuit to account for distributed substrate coupling. Layout + process information used in closed form calculation of the model parameters. *S. Jenei et al., IEEE Journal of Solid-State Circuits, January 2002

BEOL High Q Inductors BEOL Inductors In-house RF Model

RF circuit demonstrators Voltage-Controlled Oscillator (VCO) * D. Linten et al. Symposium on VLSI Circuits, June, 2004 Schematic Micrograph MIM Capacitors Junction Varactors BEOL High Q Inductors NMOS Transistors

RF circuit demonstrators Voltage-Controlled Oscillator (VCO) Only possible with accurate device models and careful circuit design!!!

Conclusions A fully integrated RF CMOS technology fabricated in a 90nm RF CMOS FEOL with High- Q passive components processed on a standard 5LM Cu/Oxide BEOL, has been presented. Accurate modelling of the active a passive devices made possible RF circuit design. RF CMOS can definitely become the technology of choice for large volume RF applications and Mixed-signal SoC platforms.

IMEC P-line for processing the devices Flemish IWT for financial support The European commission in the framework of IST IMPACT for the financial supports Acknowledgments

D.Linten et al. Low-power 5 GHz LNA and VCO in 90 nm RF CMOS, Symposium on VLSI Circuits, June, 2004 W.Jeamsaksiri et al. Integration of a 90nm RF CMOS technology (200GHz fmax - 150GHz fT NMOS) demonstrated on a 5GHz LNA, Symposium on VLSI Technology, June, 2004 W.Jeamsaksiri et al. Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors, IEEE Transactions on Electron Devices, March, 2003 D.Linten et al. A 5GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS, Accepted for publication on the European Solid-State Circuits Conference, ESSCIRC, September V.C. Venezia et al. The RF potential of high-performance 100nm CMOS technology, European Solid-State Device Research Conference, ESSDERC, September M. Jurczak et al. Elevated Co-silicide for sub-100nm High Performance and RF CMOS, European Solid-State Device Research Conference, ESSDERC, September List of related publications

D.Linten et al. A 328 mW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor, Accepted for publication on the Custom Integrated Circuits Conference, CICC, October S. Thijs et al. Implementation of Inductor Based ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS – Concepts, constraints and Solutions, Accepted for publication on the Electrical Overstress and Electrostatic Discharge Symposium, EOS/ESD, September S. Thijs et al. Impact of Elevated Source Drain Architecture on ESD Protection Devices for a 90nm CMOS Technology Node, Electrical Overstress and Electrostatic Discharge Symposium, EOS/ESD, September D.Linten et al. Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain, European Solid-State Device Research Conference, ESSDERC, September D.Linten et al. Influence of Back-End architecture on the performance of RF CMOS VCOs, Southwest Symposium on Mixed-Signal Design, February List of related publications W.Jeamsaksiri et al. Optimal frequency range selection for full C-V characterization above 45MHz for ultra thin (1.2-nm) nitrided oxide MOSFETs, International Conference in Microelectronic Test Structures, ICMTS, March, 2004

M. Ferndahl et al. 40 and 60 GHz Frequency Doublers in 90-nm CMOS, International Microwave Symposium, MTT-S, June G.J. Garchon et al. Wafer-Level Packaging Technology for High-Q On-Chip Inductors and Transmission Lines, IEEE Transactions on Microwave Theory and Techniques, April G.J. Garchon et al. High-Q above-IC inductors and transmission lines - comparison to Cu back-end performance, Electronic Components and Technology Conference, ECTC, June G.J. Garchon et al. Wafer-Level Packaging Technology for Extended Global Wiring and Inductors, European Solid-State Device Research Conference, ESSDERC, September M. Ferndahl et al. The influence of the gate leakage current and the gate resistance on the noise and gain performances of 90-nm CMOS for micro and millimeter-wave frequencies, International Microwave Symposium, MTT-S, June G.J. Garchon et al. High-Q RF Inductors on standard Silicon realized using wafer- level packaging techniques, International Microwave Symposium, MTT-S, June List of related publications

European IST IMPACT project Technology development (WP3) Devices modelling (WP2) Circuits design (WP1) IMEC Philips PITS IMEC Philips Research IMEC Ericsson Chalmers University