Sept 2005 Project: IEEE P802.15 Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [Data modulation simulation results] Date Submitted: [7 Sept 2005] Source: [Francois Chin, Wong Sai Ho, Sam Kwok, Lei Zhongding, Peng Xiaoming] Company: [Institute for Infocomm Research, Singapore] Address: [21 Heng Mui Keng Terrace, Singapore 119613] Voice: [65-68745687] E-Mail: [chinfrancois@i2r.a-star.edu.sg] Abstract: [802.15.4a devices link performance in multipath channels and SOP scenarios] Purpose: [Assist the group in the selection of a modulation scheme] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15. Francois Chin (I2R)

Simulated Modulation Options Sept 2005 Simulated Modulation Options Option I Francois Chin (I2R)

Simulated Modulation Options Sept 2005 Simulated Modulation Options Option II Francois Chin (I2R)

Simulated Modulation Options Sept 2005 Simulated Modulation Options Option 7 / 8 / 9 PRFpeak (MHz) Coherent Non-Coherent (with ½ rate CC) (Option 7) (without ½ rate CC) (Option 8) (Option 9) 30.875 Same as Option II 2 coded bit / 32 chip (4-ary 32-TOK sequence) 4 info. bit / 128 chip (based on 16-ary 32-TOK sequence) (based on 16-ary 127-TOK sequence) 61.75 Not Applicable 4 info. bit / 256 chip 247 4 info. bit / 1024 chip Francois Chin (I2R)

Simulated Modulation Options Sept 2005 Simulated Modulation Options Option 1 - burst PPM + 1/2-rate CC Option 2 – Binary Orthogonal Keying (16-chip) + 1/2-rate CC Option 7 – 4-ary Orthogonal Keying (32-chip) + 1/2-rate CC Option 8 – 16-ary Orthogonal Keying (32-chip) (with pulse compression) Option 8a/b/c differ in how close 4 pulses (representing one chip of the 32-chip code) cluster together Option 9 – 16-ary Orthogonal Keying (128-chip) Francois Chin (I2R)

Receiver Complexity Option 1, 2, 7 use 1/2–rate Convolution Encoding Sept 2005 Receiver Complexity Option 1, 2, 7 use 1/2–rate Convolution Encoding Option 8, 9 do not use, instead they have parallel depreader Complexity ranking: Parallel despreader for Orthogonal keying < viterbi HD < viterbi SD (in ascending order) HD x10 < SD Parallel despreader for Orthogonal keying x5? < viterbi HD Francois Chin (I2R)

Adopted SOP Simulation Scenarios Sept 2005 Adopted SOP Simulation Scenarios For each channel realization for the reference link, there is 10 channel realization for the interfering link (one for each of the 10 packets) Packet #, P Reference channel realization #, R Interfering channel realization #, Z Symbol Boundary Offset (#chip period),S P R= Ceil(P/10) Z = mod (R+ mod(P-1,10) ,100)+1 S = mod(P*99,C) Where C = # chip / symbol The chip period is 1/ 494MHz P = 1,…,1000 Francois Chin (I2R)

Adopted SOP Simulation Scenarios Sept 2005 Adopted SOP Simulation Scenarios Using Option II non-coherent scheme (PRF=30.875MHz) as example… and C = 256chip / symbol Packet #, P Reference channel realization #, R Interfering channel realization #, Z Symbol Boundary Offset (#chip period),S P R= Ceil(P/10) Z = mod (R+ mod(P-1,10) ,100)+1 S = mod(P*99,C) 001 1 2 99 002 3 198 … 010 11 222 011 65 020 12 188 021 4 31 990 9 218 991 100 61 1000 10 184 Francois Chin (I2R)

Additional Option of 2nd SOP Sept 2005 Additional Option of 2nd SOP For each channel realization for the reference link, there is 10 channel realization for the 1st and 2nd interfering link (one for each of the 10 packets) Packet #, P Reference channel realization #, R 1st Interfering channel realization #, Z Symbol Boundary Offset for 1st SOP (#chip period),S 2nd Interfering channel realization #,Y Symbol Boundary Offset for 2st SOP (#chip period),T P R= Ceil(P/10) Z = mod (R+ mod(P-1,10) ,100)+1 S = mod(P*99,C) Y = mod(mod( R + mod(P-1,10),100)+1,100)+1 T = mod(P*199,C) Where C = # chip / symbol The chip period is 1/ 494MHz P = 1,…,1000 Francois Chin (I2R)

Scenario with Additional Option of 2nd SOP Sept 2005 Scenario with Additional Option of 2nd SOP Using Option II non-coherent scheme (PRF=30.875MHz) as example… and C = 256chip / symbol Packet #, P Reference channel realization #, R 1st Interfering channel realization #, Z 1st SOP Symbol Boundary Offset (#chip period),S 2nd Interfering channel realization #, Y 2nd SOP Symbol Boundary Offset (#chip period),T P R= Ceil(P/10) Z = mod (R+ mod(P-1,10) ,100)+1 S = mod(P*99,C) Y = mod (R+ mod(P-1,10) ,100)+2 T = mod(P*199,C) 001 1 2 99 3 199 002 198 4 142 … 010 11 222 12 011 65 141 020 188 13 140 021 31 5 83 990 9 218 10 146 991 100 61 89 1000 184 88 Francois Chin (I2R)

Simulation Parameters Sept 2005 Simulation Parameters Sampling Rate = 494MHz Simulation Parameters 1000 packets for each CMx 10 packets for each of 100 realization channels in CMx for the reference link Channel realisations - CM1 and CM8 Includes 1-SOP performance Types of receiver - Coherent Receiver and Energy Detector Acquisition assumed for both receivers Coherent receiver – 4-tap RAKE fingers ½ rate viterbi decoder – both SD and HD Non-coherent receiver simple symbol energy detector for Option I 1-tap RAKE finger for Option 8 4-tap RAKE fingers for Options 2,7,9 Francois Chin (I2R)

Coherent Receiver Performance Sept 2005 Coherent Receiver Performance Francois Chin (I2R)

Common Signaling: AWGN Performance (Coherent) Sept 2005 Common Signaling: AWGN Performance (Coherent) Francois Chin (I2R)

Observation & Comments Sept 2005 Observation & Comments AWGN performance (Coherent) Viterbi SD > HD Option 1~ Option 2 Option 7 > Option 2 Both have ½-rate CC As 4-ary Orthogonal keying > Binary Orthogonal keying Option 8 ~ Option 9 > Option 7 As 16-ary Orthogonal keying without ½-rate CC > 4-ary Orthogonal keying with ½-rate CC Antipodal signaling (coherent mode) the best Francois Chin (I2R)

Common Signaling: CM1 Performance (Coherent) Sept 2005 Common Signaling: CM1 Performance (Coherent) Francois Chin (I2R)

Observation & Comments Sept 2005 Observation & Comments CM1 performance (Coherent) Similar to AWGN performance, except ~1.5dB degradation (due to limited RAKE energy capture) Viterbi SD > HD Option 2 > Option 1 Pulses distributed in symbol > pulses cluster together in symbol? Option 7 > Option 2 Both have ½-rate CC As 4-ary Orthogonal keying > Binary Orthogonal keying Option 8 ~ Option 9 > Option 7 As 16-ary Orthogonal keying without ½-rate CC > 4-ary Orthogonal keying with ½-rate CC Antipodal signaling (coherent mode) the best Francois Chin (I2R)

1-SOP Performance in CM1 (Coherent) Sept 2005 1-SOP Performance in CM1 (Coherent) Francois Chin (I2R)

2-SOP Performance in CM1 (Coherent) Sept 2005 2-SOP Performance in CM1 (Coherent) Francois Chin (I2R)

Observation & Comments Sept 2005 Observation & Comments 1 & 2-SOP CM1 performance (Coherent) Viterbi SD > HD Option 7 ~ Option 2 >< Option 1 Antipodal signaling (coherent mode) ~ Option 8 ~ Option 9 > Option 7 For SOP, interference suppression via longer spreading more crucial, i.e. Long spreading + Ortho. Keying > short spreading + conv. coding Francois Chin (I2R)

Common Signaling: CM8 Performance (Coherent) Sept 2005 Common Signaling: CM8 Performance (Coherent) Francois Chin (I2R)

Observation & Comments Sept 2005 Observation & Comments 1 & 2-SOP CM8 performance (Coherent) Option 8 ~ Option 9 > Option 7 > Antipodal signaling (coherent mode) > Option 2 > Option 1 For long channel delay spread, inter-finger-interference suppression via longer spreading more crucial, i.e. Long spreading + Ortho. Keying > short spreading + conv. coding Francois Chin (I2R)

1-SOP Performance in CM8 (Coherent) Sept 2005 1-SOP Performance in CM8 (Coherent) Francois Chin (I2R)

2-SOP Performance in CM8 (Coherent) Sept 2005 2-SOP Performance in CM8 (Coherent) Francois Chin (I2R)

Observation & Comments Sept 2005 Observation & Comments 1 & 2-SOP CM8 performance (Coherent) Option 8 ~ Option 9 > Option 7 > Antipodal signaling (coherent mode) > Option 2 >< Option 1 For SOP, SOP interference suppression via longer spreading more crucial, i.e. Long spreading + Ortho. Keying > short spreading + conv. coding Francois Chin (I2R)

Summary – Coherent Receiver Performance Sept 2005 Summary – Coherent Receiver Performance longer spreading is crucial for suppressing inter-path-interference, especially for long channel delay spread longer spreading is crucial for suppressing SOP interference Longer spread code can be achieved via multiple bit per symbol using orthogonal keying Francois Chin (I2R)

Non-Coherent Receiver Performance Sept 2005 Non-Coherent Receiver Performance Francois Chin (I2R)

AWGN Performance (Energy Detector) Sept 2005 AWGN Performance (Energy Detector) Francois Chin (I2R)

CM1 Performance (Energy Detector) Sept 2005 CM1 Performance (Energy Detector) Francois Chin (I2R)

1-SOP Performance in CM1 (Energy Detector) Sept 2005 1-SOP Performance in CM1 (Energy Detector) Francois Chin (I2R)

CM8 Performance (Energy Detector) Sept 2005 CM8 Performance (Energy Detector) Francois Chin (I2R)

1-SOP Performance in CM8 (Energy Detector) Sept 2005 1-SOP Performance in CM8 (Energy Detector) Francois Chin (I2R)

Sept 2005 Recommendation Francois Chin (I2R)

Backup: Modulation Schemes Options Sept 2005 Backup: Modulation Schemes Options Francois Chin (I2R)

Modulation & Coding (Option 7) Sept 2005 Modulation & Coding (Option 7) Coded Bits Bit-to- Symbol Symbol- to-Chip Symbol Repetition Pulse Generator Scrambling {0,1,-1} Ternary Sequence Bit to symbol mapping: group every 2 coded bits into a symbol (after ½ rate Conv Encoding) Symbol-to-chip mapping: Each 2-bit symbol is mapped to one of 4 32-chip sequence, according to 4-ary Ternary Orthogonal Keying Symbol Repetition: for data rate and range scalability Scrambling: with bipolar sequence @ 30.875MHz, to suppress cross correlation sidelobes due to excessive delay spread Pulse Genarator: Transmit Ternary pulses @ 30.875MHz Francois Chin (I2R)

PBTS Seq #1 1 zero padding Symbol-to-Chip Mapping (Option 7): Sept 2005 Symbol-to-Chip Mapping (Option 7): Gray coded 4-ary Ternary Orthogonal Keying Symbol Cyclic shift to right by n chips, n= 32-Chip value 00 + 0 + + 0 0 0 - + - + + 0 0 + + 0 + 0 0 - 0 0 0 0 - 0 + 0 - - 0 01 8 0 0 - 0 + 0 - - + 0 + + 0 0 0 - + - + + 0 0 + + 0 + 0 0 - 0 0 0 11 16 + 0 + 0 0 - 0 0 0 0 - 0 + 0 - - + 0 + + 0 0 0 - + - + + 0 0 + 0 10 24 - + - + + 0 0 + + 0 + 0 0 - 0 0 0 0 - 0 + 0 - - + 0 + + 0 0 0 0 PBTS Seq #1 1 zero padding Francois Chin (I2R)

Modulation & Coding (Option 8) Sept 2005 Modulation & Coding (Option 8) Info. Bits Bit-to- Symbol Symbol- to-Chip Symbol Repetition Pulse Generator Scrambling {0,1,-1} Ternary Sequence Bit to symbol mapping: group every 4 information bits into a symbol (No ½ rate Conv Encoding) Symbol-to-chip mapping: Each 4-bit symbol is mapped to one of 16 N-chip sequence, according to 16-ary Ternary Orthogonal Keying Symbol Repetition: for data rate and range scalability Scrambling: with bipolar sequence @ PRFpeak, to suppress cross correlation sidelobes due to excessive delay spread Pulse Genarator: Transmit Ternary pulses @ PRFpeak(either 30.875, 61.75 or 247MHz) Francois Chin (I2R)

N-Chip value before Scrambling Sept 2005 Symbol-to-Chip Mapping (Option 8): Gray coded 16-ary Ternary Orthogonal Keying Symbol Cyclic shift N-Chip value before Scrambling 0000 +0++000-+-++00++0+00-0000-0+0--0 0001 2 --+0++000-+-++00++0+00-0000-0+00 0011 4 +0--+0++000-+-++00++0+00-0000–00 0010 6 –0+0--+0++000-+-++00++0+00-00000 0110 8 00-0+0--+0++000-+-++00++0+00-000 0111 10 0000-0+0--+0++000-+-++00++0+00–0 0101 12 0-0000-0+0--+0++000-+-++00++0+00 0100 14 +00-0000-0+0--+0++000-+-++00++00 1100 16 +0+00-0000-0+0--+0++000-+-++00+0 1101 18 0++0+00-0000-0+0--+0++000-+-++00 1111 20 +00++0+00-0000-0+0--+0++000-+-+0 1110 22 -++00++0+00-0000-0+0--+0++000-+0 1010 24 -+-++00++0+00-0000-0+0--+0++0000 1011 26 00-+-++00++0+00-0000-0+0--+0++00 1001 28 +000-+-++00++0+00-0000-0+0--+0+0 1000 30 0++000-+-++00++0+00-0000-0+0--+0 PRFpeak (MHz) N-chip / symbol What +,-,0 represents 30.875 (Opt 8a) 128 + = ++++ - = ---- 0 = 0000 61.75 (Opt 8b) 256 + = ++++0000 - = ----0000 0 = 00000000 247 (Opt 8c) 1024 + = ++++0000 00000000 00000000 00000000 - = ----0000 00000000 0 = 00000000 00000000 Francois Chin (I2R)

Modulation & Coding (Option 9) Sept 2005 Modulation & Coding (Option 9) Info. Bits Bit-to- Symbol Symbol- to-Chip Symbol Repetition Pulse Generator Scrambling {0,1,-1} Ternary Sequence Bit to symbol mapping: group every 4 information bits into a symbol (No ½ rate Conv Encoding) Symbol-to-chip mapping: Each 4-bit symbol is mapped to one of 16 128-chip sequence, according to 16-ary Ternary Orthogonal Keying Symbol Repetition: for data rate and range scalability Scrambling: with bipolar sequence @ 30.875MHz, to suppress cross correlation sidelobes due to excessive delay spread Pulse Genarator: Transmit Ternary pulses @ 30.875MHz Francois Chin (I2R)

PBTS Seq#1 Symbol-to-Chip Mapping (Option 9): Sept 2005 Symbol-to-Chip Mapping (Option 9): Gray coded 16-ary Ternary Orthogonal Keying Symbol Cyclic shift 128-Chip value 0000 0000+++-++-0+0+0-00++00-++0+--0-00+0++000+-0+++-0-+0-0--0--00+00 +000+-+0000+0-++--00+0+0+--00--0+000-00+-+-000-0-0000++00000+000 0001 8 00000+000000+++-++-0+0+0-00++00-++0+--0-00+0++000+-0+++-0-+0-0-- 0--00+00+000+-+0000+0-++--00+0+0+--00--0+000-00+-+-000-0-0000++0 0011 16 0-0000++00000+000000+++-++-0+0+0-00++00-++0+--0-00+0++000+-0+++- 0-+0-0--0--00+00+000+-+0000+0-++--00+0+0+--00--0+000-00+-+-000-0 0010 24 ... 0110 32 0111 40 0101 48 0100 56 1100 64 1101 72 1111 80 1110 88 1010 96 1011 104 1001 112 0-00++00-++0+--0-00+0++000+-0+++-0-+0-0--0--00+00 +000+-+0000+0- ++--00+0+0+--00--0+000-00+-+-000-00000++00000+000000+++-++-0+0+0 1000 120 -++-0+0+0-00++00-++0+--0-00+0++000+-0+++-0-+0-0--0--00+00 +000+- +0000+0-++--00+0+0+--00--0+000-00+-+-000-00000++00000+000000+++0 PBTS Seq#1 Francois Chin (I2R)