1. doc.: IEEE 802.15-<doc#>
<month year>
doc.: IEEE <doc#>
Sept 2004
Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs)
Submission Title: [Comparison of IEEE b High Rate Alt-PHY proposals]
Date Submitted: [13 Sept, 2004]
Source: [Francois Chin] Company: [Institute for Infocomm Research, Singapore]
Address: [21 Heng Mui Keng Terrace, Singapore ]
Voice: [ ] FAX: [ ]
Re: [Response to the call for proposal of IEEE b, Doc Number: b]
Abstract: [This presentation compares all proposals for the IEEE b PHY standard.]
Purpose: [Proposal to IEEE b Task Group]
Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
Francois Chin, Institute for Infocomm Research (I2R)
<author>, <company>

2. Summary of Proposed Code Sets
Sept 2004
Code Set
A32
B16 C8 D8
E16
F31
G16
Description
32-chip
(15.4 original)
16-chip
8-chip for Coh. Chip Despreading
8-chip for Diff. Chip Despreading
Orthogonal 16-DSSS
PSSS
16-chip for Coh. Chip Despreading
Proposer
Motorola / Freescale
I2R
Helicomm
Dr. Wolf & Assoc.
Doc #
04-189
04-403
04-507(new)
04-314
04-121
Sym-Chip mapping
Cyclic & Odd Bit Inversion
(COBI)
Orthogonal
Multi-code
Bit/sym 4 3 15
Chip/Sym 32 16 8
31+1 cyclic extension
16+1 cyclic extension
Bit/chip
0.125
0.25
0.5
0.375
~0.47
~0.24
Root Sequence
D9C3522E
3AFC 5C 45
N.A.
08B3E375
2F53
Coh. Chip Despreading (CCD)
Yes
Differential Chip Despreading
(DCD) No
Francois Chin, Institute for Infocomm Research (I2R)

3. BER Performance Comparison
Sept 2004
BER Performance Comparison
Code Sequence
A32 D8
B16 C8
E16
Performance of proposed 16-chip and 8-chip code sets, in comparison with original PHY length-32 Symbol-to-Chip performance and Orthogonal DSSS sequences as in b-enhanced-oqpsk-modulation-with-orthogonal-dsss-sequences
Francois Chin, Institute for Infocomm Research (I2R)

4. Comparison Methodology
Sept 2004
Comparison Methodology
Multipath robustness performance
Bandwidth efficiency (bps / Hz)
RF requirement
Memory requirement
Francois Chin, Institute for Infocomm Research (I2R)

5. Multipath Realisations
Sept 2004
Multipath Realisations
100 Channel Realisations at each RMS Delay Spread
Francois Chin, Institute for Infocomm Research (I2R)

6. Multipath Realisations
Sept 2004
Multipath Realisations
100 Channel Realisations at each RMS Delay Spread
Francois Chin, Institute for Infocomm Research (I2R)

7. Sept 2004
Candidates for Multipath Performance Comparison (using Coherent Chip Despreading)
Code Set
A32
B16 D8
Description
32-chip
(15.4 original)
16-chip
8-chip for Diff. Chip Despreading
Proposer
Motorola / Freescale
I2R
Doc #
04-189
04-403
Sym-Chip mapping
Cyclic & Odd Bit Inversion
(COBI)
Bit/sym 4 3
Chip/Sym 32 16 8
Bit/chip
0.125
0.25
0.375
Root Sequence
D9C3522E
3AFC 45
Coh. Chip Despreading (CCD)
Yes
Differential Chip Despreading
(DCD)
Francois Chin, Institute for Infocomm Research (I2R)

8. Proposed Symbol-to-Chip Mapping (16-chip Code Set B16)
Sept 2004
Proposed Symbol-to-Chip Mapping (16-chip Code Set B16)
Decimal Value
Binary Symbol
Chip Value
0000
(Root - 3AFC) 1
1000 2
0100 3
1100 4
0010 5
1010 6
0110 7
1110 8
0001 9
1001 10
0101 11
1101 12
0011 13
1011 14
0111 15
1111
The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Francois Chin, Institute for Infocomm Research (I2R)

9. Other Root Sequences (16-chip Code Set B16)
Sept 2004
Other Root Sequences (16-chip Code Set B16)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10: ….
Francois Chin, Institute for Infocomm Research (I2R)

10. Proposed Symbol-to-Chip Mapping (8-chip Code Set D8)
Sept 2004
Proposed Symbol-to-Chip Mapping (8-chip Code Set D8)
3-bit / symbol mapping
Decimal Value
Binary Symbol
Chip Value
000
(root – 45h) 1
100 2
010 3
110 4
001 5
101 6
011 7
111
The sequences are related to each other through cyclic shifts and/or conjugation (i.e., inversion of odd-indexed chip values)
Francois Chin, Institute for Infocomm Research (I2R)

11. Other Root Sequences (8-chip Code Set D8)
Sept 2004
Other Root Sequences (8-chip Code Set D8)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:
Francois Chin, Institute for Infocomm Research (I2R)

12. AWGN Performance (Differential Chip Despreading)
Sept 2004
Performance comparison
32-chip ~ 8-chip (3/8 bit/chip) > 16-chip
Francois Chin, Institute for Infocomm Research (I2R)

13. Multipath Performance (Differential Chip Despreading)
Sept 2004
Performance - 32-chip (1/8 bit/chip) > 16-chip (1/4 bit/chip) > 8-chip (3/8 bit/chip)
Francois Chin, Institute for Infocomm Research (I2R)

14. Multipath Performance (Differential Chip Despreading)
Sept 2004
@ 1us RMS delay spread (RMS delay spread / chip period > 0.3), no apparent BER floor
Francois Chin, Institute for Infocomm Research (I2R)

15. Multipath Performance (Differential Chip Despreading)
Sept 2004
@ 2us RMS delay spread (RMS delay spread / chip period < 0.6), apparent BER floor
Francois Chin, Institute for Infocomm Research (I2R)

16. Multipath Performance Summary (Differential Chip Despreading)
Sept 2004
Multipath Performance Summary (Differential Chip Despreading)
When RMS delay spread / chip period > 0.3, inter–chip interference (ICI) sets in
Sequence length helps, but does not eliminate ICI ….
Coherent chip despreading is explored next ….
Francois Chin, Institute for Infocomm Research (I2R)

17. Sept 2004
Candidates for Multipath Performance Comparison (using Coherent Chip Despreading)
Code Set C8
E16
F31
G16
Description
8-chip for Coh. Chip Despreading
Orthogonal 16-DSSS
PSSS
16-chip for Coh. Chip Despreading
Proposer
I2R
Helicomm
Dr. Wolf & Assoc.
Doc #
04-507
04-314
04-121
04-507(new)
Sym-Chip mapping
Cyclic & Odd Bit Inversion
Orthogonal
Multi-code
Bit/sym 4 15
Chip/Sym
8+1 cyclic extension
16+1 cyclic extension
31+1 cyclic extension
Bit/chip
0.44
0.25
~0.47
~0.24
Root Sequence 5C
N.A.
08B3E375
2F53
Coh. Chip Despreading (CCD)
Yes
Differential Chip Despreading
(DCD) No
Francois Chin, Institute for Infocomm Research (I2R)

18. Other Root Sequences (8-chip C8 for Coherent Despreading only)
Sept 2004
Other Root Sequences (8-chip C8 for Coherent Despreading only)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:
Francois Chin, Institute for Infocomm Research (I2R)

19. DSSS Sequence E16 Sept 2004 Source doc.: IEEE 802.15-04-0314-02-004b
Decimal Symbol
Binary Symbol
Chip Values 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Source doc.: IEEE b
Francois Chin, Institute for Infocomm Research (I2R)

20. PSSS Sequence F31 (15 bit/32 chip)
Sept 2004
PSSS Sequence F31 (15 bit/32 chip)
Source doc.: IEEE b
No Pre-coding is employed in this simulation
Francois Chin, Institute for Infocomm Research (I2R)

21. Other Root Sequences (8-chip G16 for Coherent Despreading only)
Sept 2004
Other Root Sequences (8-chip G16 for Coherent Despreading only)
The following Root Sequences are found through exhaustive search with identical low cross correlation and autocorrelation, in base 10:
Francois Chin, Institute for Infocomm Research (I2R)

22. Multipath Performance (Coherent Chip Despreading)
Sept 2004
For DSSS, 2 RAKE fingers are required to over BER floor
Francois Chin, Institute for Infocomm Research (I2R)

23. Multipath Performance (Coherent Chip Despreading)
Sept 2004
For PSSS, 2 RAKE fingers are required to over BER floor
Francois Chin, Institute for Infocomm Research (I2R)

24. Multipath Performance (Coherent Chip Despreading)
Sept 2004
For 8-chip COBI Sequence, 2 RAKE fingers are required to over BER floor
Francois Chin, Institute for Infocomm Research (I2R)

25. Multipath Performance (Coherent Chip Despreading)
Sept 2004
For 16-chip COBI Sequence, 2 RAKE fingers are required to over BER floor
Francois Chin, Institute for Infocomm Research (I2R)

26. Coherent Receiver Multipath Performance
Sept 2004
Given receiver with 2 RAKE fingers
all Sequence gives 2dB ~ 6dB gain by using additional Cyclic-Prefix chip to achieve best performance / data rate trade off
PSSS (31+1 chip) > COBI sequence (8+1 chip) > COBI sequence (16+1 chip) > DSSS Sequence (16 +1 chip); all coding schemes are within 3dB from each other
Francois Chin, Institute for Infocomm Research (I2R)

27. Coherent Receiver Multipath Performance
Sept 2004
Coherent Receiver Multipath Performance
General performance comparison:
PSSS (31+1 chip) > COBI sequence (8+1 chip) > COBI sequence (16+1 chip) > DSSS Sequence (16 +1 chip)
What leads to Multipath robustness?
Frequency selectivity leads to Inter-chip interference, and that is the killer….
To overcome, code must have good autocorrelation properties, i.e. low sidelodes.
Francois Chin, Institute for Infocomm Research (I2R)

28. How these codes achieve Multipath robustness?
Sept 2004
How these codes achieve Multipath robustness?
PSSS, uses flexibility in amplitude to achieve zero auto-correlation throughout
COBI, maintain constant module, can at best achieve zero auto-correlation within 2 chips from cor. Peak; that is good enough to handle ICI of upto 2 chip periods
DSSS, comprising Walsh sequences, has auto-correlation sidelodes
Francois Chin, Institute for Infocomm Research (I2R)

29. Multipath Performance Summary (Coherent Chip Despreading)
Sept 2004
Multipath Performance Summary (Coherent Chip Despreading)
To combat inter-chip interference due to relatively large channel delay spread (RMS delay spread / chip period ~ 0.6), 2 recommendations are:
RAKE combining (with 2 fingers) in receiver to combine path diversity; (this does not affect standard)
One additional chip extension to the chip sequence to avoid inter-symbol interference (this one does)
With the 2 recommendations,
@ BER = 10-5 (PER ~ 127 byte-packet), all three candidates (namely, DSSS, PSSS (without pre-coding) and 8-chip COBI Sequence) are working within 3dB difference, under large channel delay spread
Francois Chin, Institute for Infocomm Research (I2R)

30. Sept 2004
Candidates for Multipath Performance Comparison (using Coherent Chip Despreading)
Code Set C8
E16
F31
G16
Description
8-chip for Coh. Chip Despreading
Orthogonal 16-DSSS
PSSS
16-chip for Coh. Chip Despreading
Proposer
I2R
Helicomm
Dr. Wolf & Assoc.
Doc #
(new)
04-314
04-121
Sym-Chip mapping
Cyclic & Odd Bit Inversion
Orthogonal
Multi-code
Bit/sym 4 15
Chip/Sym
8+1 cyclic extension
16+1 cyclic extension
31+1 cyclic extension
Bit/chip
0.44
0.25
~0.47
~0.24
Multipath performance
Better
Good
Best
Memory requirement
Low
Single sequence
High
16 sequence
RF linearity requirement
Moderate ~ high
Note : Red - desirable
Francois Chin, Institute for Infocomm Research (I2R)

31. Code Sequence Recommendations
Sept 2004
Code Sequence Recommendations
Multipath robustness vs complexity
Differential chip despreading can only support multipath channels with RMS delay spread around 1us with chip rate 300kcps (RMS delay spread-chip period ~ 0.3, that means ~ 300ns with half rate 1Mcps, proposed in 915MHz)
As multipath robustness is vital, and differential chip despreading does not perform well under channels with excessive delay spread, coherent chip despreading is needed to ensure coverage
8-chip & 16-chip COBI sequence is recommended for its low RF linearity requirement, high bandwidth efficiency and low memory requirement
Francois Chin, Institute for Infocomm Research (I2R)

32. Recommendations for low GHz Bands
Sept 2004
Recommendations for low GHz Bands
Ch #0
868MHz band
Ch #1-10
906 – 924 MHz band
Bandwidth
600 kHz
2 MHz
Recommended Code Set
8-chip COBI
C8 (4/9 bit/chip)
16-chip COBI
G16 (4/17 bit/chip)**
Receiver
Cohent Chip Despreading
Chip rate
300kcps
400kcps
1Mcps
Pulse shape
Half-sine
Modulation
OQPSK
Data rate
133.3 kbps
177.8 kbps
444 kbps
235 kbps
** Code sequence & related multipath robustness performance available soon
Francois Chin, Institute for Infocomm Research (I2R)