MIPS Coding Continued.

Slides:



Advertisements
Similar presentations
MIPS Assembly Tutorial
Advertisements

1 Lecture 3: MIPS Instruction Set Today’s topic:  More MIPS instructions  Procedure call/return Reminder: Assignment 1 is on the class web-page (due.
Goal: Write Programs in Assembly
Lecture 5: MIPS Instruction Set
MIPS assembly. Review  Lat lecture, we learnt  addi,  and, andi, or, ori, xor, xori, nor,  beq, j, bne  An array is stored sequentially in the memory.
CS/COE0447 Computer Organization & Assembly Language
Branches Two branch instructions:
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /15/2013 Lecture 11: MIPS-Conditional Instructions Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER.
MIPS processor continued. Review Different parts in the processor should be connected appropriately to be able to carry out the functions. Connections.
CS1104 – Computer Organization PART 2: Computer Architecture Lecture 5 MIPS ISA & Assembly Language Programming.
Chapter 2 Instructions: Language of the Computer
Assembly Process. Machine Code Generation Assembling a program entails translating the assembly language into binary machine code This requires more than.
Comp Sci instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction.
Computer Architecture CPSC 321 E. J. Kim. Overview Logical Instructions Shifts.
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
CS 300 – Lecture 6 Intro to Computer Architecture / Assembly Language Instructions.
April 23, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 9: Assemblers, Linkers, and Loaders * Jeremy R. Johnson Mon. April 23,
Lecture 4: MIPS Instruction Set
MIPS coding. Review Shifting – Shift Left Logical (sll) – Shift Right Logical (srl) – Moves all of the bits to the left/right and fills in gap with 0’s.
Computer Architecture CSE 3322 Lecture 3 Assignment: 2.4.1, 2.4.4, 2.6.1, , Due 2/3/09 Read 2.8.
MIPS coding. slt, slti slt $t3, $t1, $t2 – set $t3 to be 1 if $t1 < $t2 ; else clear $t3 to be 0. – “Set Less Than.” slti $t3, $t1, 100 – set $t3 to be.
Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.
The Assembly Process Computer Organization and Assembly Language: Module 10.
Control Structures Computer Organization I 1 October 2009 © McQuain, Feng & Ribbens Conditional Control Structure if ( i < j ) goto A; else.
MIPS Assembly Language Programming
Computer Architecture & Operations I
MIPS Assembly.
Computer Architecture Instruction Set Architecture
MIPS Instruction Set Advantages
COMPUTER ARCHITECTURE & OPERATIONS I
MIPS Coding Continued.
Lecture 4: MIPS Instruction Set
ELEN 468 Advanced Logic Design
MIPS instructions.
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
Conditional Branches What distinguishes a computer from a simple calculator is its ability to make decisions Decisions are made using the if statement,
Computer Architecture (CS 207 D) Instruction Set Architecture ISA
Computer Architecture & Operations I
Instructions for Making Decisions
CS170 Computer Organization and Architecture I
The University of Adelaide, School of Computer Science
MIPS processor continued
MIPS coding.
Instructions - Type and Format
Lecture 4: MIPS Instruction Set
Computer Architecture & Operations I
MIPS Processor.
MIPS Instruction Encoding
ECE232: Hardware Organization and Design
MIPS coding.
MIPS processor continued
MIPS Instruction Encoding
Instruction encoding The ISA defines Format = Encoding
Lecture 5: Procedure Calls
MIPS coding.
Review.
MIPS Coding.
Instructions and Conditional Execution
Flow of Control -- Conditional branch instructions
3.
MIPS Coding.
COMS 361 Computer Organization
COMS 361 Computer Organization
MIPS Assembly.
Flow of Control -- Conditional branch instructions
MIPS coding.
MIPS assembly.
MIPS Processor.
MIPS instructions.
Conditional Branching (beq)
Presentation transcript:

MIPS Coding Continued

Exercise 1 Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(A[i], B[i]) for all 0<= i <= 9. 4/22/2019 week04-3.ppt

Exercise 1 Suppose we have three arrays, A, B, C, all of size 10. Now we want to set C[i] = min(A[i], B[i]) for all 0<= i <= 9. First, we need a loop to walk through the elements (done before) Second, we need to be able to read the elements (done before) Third, we need to be able to compare two numbers (done before) Fourth, we need to write back to the memory (easy) So, first write the loop. Then, write codes to read the elements. Then, compare with if else. Then, write back. 4/22/2019 week04-3.ppt

add $t5, $t4,$s0 # $t5 will have the address of A[i] .data A: .word 12, 34, 67, 1, 45, 90, 11, 33, 67, 19 B: .word 90, 2, 93, 66, 8, 120, 121,11, 33, 9 C: .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 .text .globl main main: la $s0, A la $s1, B la $s2, C li $s3, 10 li $t0, 0 # using $t0 as i LOOP: sll $t4, $t0, 2 # $t4 = i * 4 add $t5, $t4,$s0 # $t5 will have the address of A[i] lw $t1, 0($t5) # $t1 has A[i] add $t6, $t4,$s1 # $t6 will have the address of B[i] lw $t2, 0($t6) # $t2 has B[i] slt $t5, $t1, $t2 # set $t5 to be 1 if A[i] < B[i] beq $t5, $0, L1 # if $t5 == 0, goto L1. in this case, A[i] >= B[i] ori $t8, $t1, 0 # setting $t8 to be A[i] j L2 # always remember to jump in an if else! L1: ori $t8, $t2, 0 # setting $t8 to be B[i] L2: add $t6, $t4, $s2 # now $t6 has the address of C[i] sw $t8, 0($t6) # now C[i] has the minimum of A[i] and B[i] addi $t0, $t0, 1 # i ++ bne $t0, $s3, LOOP # go back if not yet 10 times done: li $v0,10 syscall

Representing Instructions in Computers 4/22/2019 Representing Instructions in Computers Note that computers only have 0’s and 1’s Before we can load MIPS instructions into memory, they need to be translated into machine instructions, which consist of only 0’s and 1’s In other words, we need to encode or represent instructions The symbolic representation of machine instructions is called assembly language The binary representation of instructions is called machine language A sequence of instructions in binary form is called machine code 4/22/2019 CDA3100 CDA3100

4/22/2019 Example 4/22/2019 CDA3100 CDA3100

MIPS Instruction Encoding Each MIPS instruction is exactly 32 bits R-type (register type) I-type (immediate type) J-type (jump type) op rs rt rd shamt funct op rs rt 16 bit address or constant op 26 bit address 4/22/2019 CDA3100

R-Type Encoding Encoding = 0x00622020 opcode rs rt rd shamt funct 1 31 opcode rs rt rd 26 25 21 20 16 15 11 10 6 5 shamt funct 1 add $4, $3, $2 Encoding = 0x00622020 4/22/2019 CDA3100

I-type Encoding Encoding = 0x8C450BB8 opcode rs rt Immediate Value 31 opcode rs rt Immediate Value 26 25 21 20 16 15 lw $5, 3000($2) Immediate 1 Encoding = 0x8C450BB8 4/22/2019 CDA3100

I-type Encoding Encoding = opcode rs rt Immediate Value rt Immediate 4/22/2019 I-type Encoding 31 26 25 21 20 16 15 opcode rs rt Immediate Value rt Immediate sw $5, 3000($2) rs 31 26 25 21 20 16 15 opcode rs rt Immediate Value Encoding = 4/22/2019 CDA3100 CDA3100

I-type Encoding Encoding = 0xAC450BB8 opcode rs rt Immediate Value 31 opcode rs rt Immediate Value 26 25 21 20 16 15 sw $5, 3000($2) Immediate 1 Encoding = 0xAC450BB8 4/22/2019 CDA3100

I-type Encoding Encoding = opcode rs rt Immediate Value rt Immediate 4/22/2019 I-type Encoding 31 26 25 21 20 16 15 opcode rs rt Immediate Value rt Immediate addi $s0, $s0, 95 rs 31 26 25 21 20 16 15 opcode rs rt Immediate Value Encoding = 4/22/2019 CDA3100 CDA3100

I-type Encoding Encoding = 0x2210005F opcode rs rt Immediate Value rt 4/22/2019 I-type Encoding 31 26 25 21 20 16 15 opcode rs rt Immediate Value rt Immediate addi $s0, $s0, 95 rs 31 26 25 21 20 16 15 1 1 1 1 1 1 1 1 1 opcode rs rt Immediate Value 1 1 1 1 1 1 1 1 1 Encoding = 0x2210005F 4/22/2019 CDA3100 CDA3100

J-type Encoding Encoding = 0x0810001F opcode Jump Address Jump Address 31 26 25 opcode Jump Address Jump Address j 0x0040007c 0x0040007c: the address of the instruction to jump to. When encoding it, take the bit 2 to bit 27. 31 26 25 1 j 0x0040007c 1 1 1 1 1 1 opcode Jump Address 1 1 1 1 1 1 1 Encoding = 0x0810001F

How to Encode Branch Instructions 4/22/2019 How to Encode Branch Instructions To encode these branch instructions, we first need to figure out the value for the associated label This will be done by the assembler Note that the MIPS has the alignment restriction, which means all the labels will be a multiple of 4 To increase the range, the address divided by 4 is actually encoded In other words, the address is in terms of words (32 bits), rather than bytes 4/22/2019 week04-3.ppt CDA3100

Encoding Conditional Branch Instructions 4/22/2019 Encoding Conditional Branch Instructions It branches the number of the instructions specified by the offset if register rs equals to register rt In the stored-program concept, we implicitly need a register to hold the address of the current instruction being executed Which is called program counter (PC) (should be called instruction address register) What is the value of PC after we finish executing the current instruction? 4/22/2019 week04-3.ppt CDA3100

Encoding Conditional Branch Instructions 4/22/2019 Encoding Conditional Branch Instructions PC-relative addressing The offset of conditional branch instructions is relative to PC + 4 Since all MIPS instructions are 4 bytes long, the offset refers to the number of words to the next instruction instead of the number of bytes 4/22/2019 week04-3.ppt CDA3100

Encoding bne Encoding = 0x16740002 opcode rs rt Immediate Value rs 4/22/2019 Encoding bne 31 26 25 21 20 16 15 opcode rs rt Immediate Value rs Label/Offset bne $19, $20, Else rt 31 26 25 21 20 16 15 1 1 1 1 1 1 1 1 opcode rs rt Immediate Value 1 1 1 1 1 1 1 1 Encoding = 0x16740002 4/22/2019 week04-3.ppt CDA3100