Department of Electrical and Computer Engineering Probabilistic modelling of performance parameters of Carbon Nanotube transistors By Yaman Sangar Amitesh Narayan Snehal Mhatre Department of Electrical and Computer Engineering

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology - Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

MOTIVATION: Why CNTFET? Dennard Scaling might not last long Increased performance by better algorithms? More parallelism? Alternatives to CMOS - FinFETs, Ge-nanowire FET, Si-nanowire FET, wrap-around gate MOS, graphene ribbon FET What about an inherently faster and less power consuming device? Yay CNTFET – faster with low power Yaman 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Carbon Nanotubes CNT is a tubular form of carbon with diameter as small as 1nm CNT is configurationally equivalent to a 2-D graphene sheet rolled into a tube. Amitesh 04/29/2014

Types of CNTs Single Walled CNT (SWNT) Double Walled CNT (DWNT) Multiple Walled CNT (MWNT) Depending on Chiral angle: Semiconducting CNT (s-CNT) Metallic CNT (m-CNT) Amitesh 04/29/2014

Properties of CNTs Strong and very flexible molecular material Electrical conductivity is 6 times that of copper High current carrying capacity Thermal conductivity is 15 times more than copper Toxicity? Amitesh 04/29/2014

CNTFET How CNTs conduct? Gate used to electrostatically induce carriers into tube Ballistic Transport Amitesh 5min 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 2 Input Nand 24.32 20.67 5.98 0.69 2 Input Nor 39.26 22.13 6.49 0.48 Yaman 3 min 04/29/2014

Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 2 Input Nand 24.32 20.67 5.98 0.69 2 Input Nor 39.26 22.13 6.49 0.48 Better delay 04/29/2014

Simulation based Comparison between CMOS and CNT technology Circuit FET Delay (In Picoseconds) Power (In uWatts) Inverter CMOS 16.58 9.81 CNT 3.78 0.25 2 Input Nand 24.32 20.67 5.98 0.69 2 Input Nor 39.26 22.13 6.49 0.48 Better delay At lower power! 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Challenges with CNT technology Unavoidable process variations Performance parameters affected Major CNT specific variations CNT density variation Metallic CNT induced count variation CNT diameter variation CNT misalignment CNT doping variation snehal 04/29/2014

Threshold voltage variation CNT density variation CNT diameter variation Current variation Threshold voltage variation 04/29/2014

CNT Misalignment CNT doping variation Changes effective CNT length Short between CNTs Incorrect logic functionality Reduction in drive current May not lead to unipolar behavior 04/29/2014

Metallic CNT induced count variation m-CNT m-CNT Current s-CNT s-CNT Excessive leakage current Increases power consumption Changes gate delay Inferior noise performance Defective functionality Vgs Snehal – 3-4 min 04/29/2014

Removal of m-CNTFETs VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later removed. Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the semiconducting nanotubes and further dissolution of m-CNTs in chloroform. Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a cutoff diameter. 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Probabilistic model of CNT count variation due to m-CNTs Probability of grown CNT count P N gs = n gs |N=n = n C n gs p s n gs p m (n− n gs ) P N gm = n gm |N=n = n C n gm p s (n− n gm ) p m n gm ps = probability of s-CNT pm = probability of m-CNT ps = 1 - pm Ngs = number of grown s-CNTs Ngm = number of grown m-CNTs N = total number of CNTs snehal 04/29/2014

Conditional probability after removal techniques Ns = number of surviving s-CNTs Nm = number of surving m-CNTs prs = conditional probability that a CNT is removed given that it is s-CNT prm = conditional probability that a CNT is removed given that it is m-CNT qrs = 1 - prs qrm = 1 -prm 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Effect of CNT count variation on ION / IOFF tuning ratio ION / IOFF is indicator of transistor leakage Improper ION / IOFF → slow output transition or low output swing Target value of ION / IOFF = 104 04/29/2014

µ(ICNT) = psµ( Is )+ pmµ(Im ) Current of a single CNT ICNT = ps Is + pmIm µ(ICNT) = psµ( Is )+ pmµ(Im ) ICNT = drive current of single CNT (type unknown) Is = drive current of single s-CNT Im = drive current of single m-CNT ps = probability of s-CNT pm = probability of m-CNT 04/29/2014

ION / IOFF ratio of CNTFET 𝐼 𝑂𝑁 𝐼 𝑂𝐹𝐹 = 𝑁 𝑠 𝐼 𝑠,𝑜𝑛 + 𝑁 𝑚 𝐼 𝑚 𝑁 𝑠 𝐼 𝑠,𝑜𝑓𝑓 + 𝑁 𝑚 𝐼 𝑚 Ns = count of s-CNT Nm = count of m-CNT Is,on = s-CNT current, Vgs = Vds = Vdd Is,off = s-CNT current, Vgs = 0 and Vds = Vdd Im = m-CNT current, Vds = Vdd 04/29/2014

ION / IOFF ratio of CNTFET µ( 𝐼 𝑂𝑁 ) µ ( 𝐼 𝑂𝐹𝐹 ) = µ( 𝑁 𝑠 ) µ( 𝐼 𝑠,𝑜𝑛 ) + µ( 𝑁 𝑚 ) µ( 𝐼 𝑚 ) µ( 𝑁 𝑠 ) µ( 𝐼 𝑠,𝑜𝑓𝑓 ) + µ( 𝑁 𝑚 ) µ( 𝐼 𝑚 ) µ (Ns) = ps (1 - prs) N µ (Nm) = pm (1 - prm) N µ( 𝐼 𝑂𝑁 ) µ ( 𝐼 𝑂𝐹𝐹 ) = 𝑝 𝑠 1 − 𝑝 𝑟𝑠 𝜇( 𝐼 𝑠,𝑜𝑛 ) + 𝑝 𝑚 1− 𝑝 𝑟𝑚 𝜇( 𝐼 𝑚 ) 𝑝 𝑠 1 − 𝑝 𝑟𝑠 𝜇( 𝐼 𝑠,𝑜𝑓𝑓 ) + 𝑝 𝑚 1− 𝑝 𝑟𝑚 𝜇(𝐼 𝑚 ) 04/29/2014

Effect of various processing parameters on the ratio µ(ION) / µ(IOFF) 𝜇( 𝐼 𝑜𝑛 ) 𝜇( 𝐼 𝑜𝑓𝑓 ) µ(ION) / µ(IOFF) is more sensitive to prm µ(ION) / µ(IOFF) = 104 for prm > 1 – 10 -4 = 99.99 % for pm = 33.33% 1- prm Snehal 5 min 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion amitesh 04/29/2014

Effect of CNT count variation on Gate delay delay= C load ∆V I drive amitesh 04/29/2014

μ(delay)≈ C load V dd μ( I drive σ(delay)≈ C load V dd μ 2 ( I drive σ( I drive ) σ(delay)≈μ(delay) σ( I drive ) μ( I drive =𝑝𝑠 σ2 𝐼𝑠 +𝑝𝑚σ2 𝐼𝑚 +𝑝𝑚𝑝𝑠 μ 𝐼𝑠 − μ 𝐼𝑚 2 σ(delay) μ(delay) = p s σ s 2 p m p s μ s 2 p s μ s = σ s 2 p m μ s 2 p s μ s 04/29/2014

Plot of σ delay μ(delay) v/s 𝜎 𝑠 𝜇 𝑠 𝜎 𝑠 𝜇 𝑠 = 0.3 σ delay μ(delay) N = 10 N = 20 N = 40 N = 30 N = 50 𝜎 𝑠 𝜇 𝑠 04/29/2014

Plot of σ delay μ(delay) v/s N 0.9 0.8 0.6 0.2 0.4 Amitesh 6 min N 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion 04/29/2014

Noise Margin of CNTFET Yaman 04/29/2014

VIL and VIH pFET nFET β n 2 V GS 𝑛 − V th n V GS n − V th n − 2kT q + E f q − 2𝐼 e −1 m = β p 2 V GS p − V th p − 2𝐼 e −1 m + 2kT q V DS p −V DS p 2 Substituting V GS n = Vin, V GS p = V DD − V in , V DS n = V out and V DS p = V out − V DD β n 2 V in − V th n V in − V th n − 2kT q + 2∆ E f q − 2𝐼 e −1 m = β p 2 2 V in − V DD − V th p − 2𝐼 e −1 m + 2kT q V out − V DD − V out − V DD 2 Differentiating with respect to Vin and substituting d V out d V in = -1 04/29/2014

VIL and VIH NML = VIL - 0 NMH = VDD – VIH For CMOS, For CNTFET, Yaman 7 8 min 04/29/2014

Overview Motivation Introduction CMOS v/s CNTFETs CNT Technology – Challenges Probabilistic model of faults Modelling performance parameters: ION / IOFF tuning ratio Gate delay Noise Margin Conclusion Yaman 2 3min 04/29/2014

CONCLUSION Modeled count variations and hence device current as a probabilistic function Studied the affect of these faults on tuning ratio and gate delay Inferred some design guidelines that could be used to judge the correctness of a process Mathematically derived noise margin based on current equations – better noise margin than a CMOS 04/29/2014

Ques 2 min