Description and Analysis of MULTIPLIERS using LAVA

Today: Describe the most common multiplier circuits In general As Lava descriptions Analyze them using Lava Self optimizing descriptions Time and size estimations

Lava advantages Efficient description of very complex structured circuits Automatically generic description (in contrast to e.g VHDL) Efficient use of formal verification Inheritance of the power of Haskell

Binary multiplication All algorithms use the ”sum of partial products” method: Possible trade-off: Many PPs – Easier generation Fewer PPs – Complex generation

Binary multiplication Decomposition of the multiplier:

Binary multiplication Partial product selection method: Pi = Si  N (shifted to the same position as Si ) Example:

Binary multiplication Two basic steps: Generation of partial products (PPG) Summation of partial products Several methods exitst for each step Famous: Booth, Wallace… Goal: To be able to combine any method for the first step with any method for the second step

Interface All PPs start from position 0 (shift by padding zeroes) Use adders whose result has the same length as the longest input (no carry-out) When carry-out is needed (only 1-bit selection), pad with one zero after

Simple PPG (1-bit selection)

Bit multiplier

Carry-propagate adder

Linear array summation

Adder tree summation

Simple multipliers

Booth’s algorithm (s-bit selection) The number of PPs is m/s s-1 adders are used in the selection

Improved Booth 2 Booth 2 selects part. prod. values from {0,N, 2N, 3N} BUT, 3N = 4N – N So, instead of 3N, select –N The next part. prod. selection has to compensate for this

New selection method

Improved Booth s The number of PPs is m/s+1 s-2 adders are used The negation of PPs can easily be integrated into the selection procedure

Improved Booth s

The carry-save adder

The carry-save array

Speed up summation with faster adders (logarithmic) Linear array has several equal-length critical paths  All adders need to be replaced The carry-save array has only ONE critical path  Replace only the final CPA

Logarithmic adder (Ladner – Fisher)

Wallace tree

Wallace tree Sums in O(log m) steps

Reducing hardware All circuits have used lots of constant bits, which need unnecessary hardware Circuits operating on constant bits can be reduced Sufficient to make the reduction in the basic gates (inv, and, nand, or, nor, xor, xnor) The reduction of the larger circuits follows automatically

Interpretations Standard: Symbolic: Non-standard…

Self-reducing gates Constant bits: low, high Everything else is variable var ”a” inv high

Reduction of larger circuits

Time estimation

Size estimation Problem with sharing:

Redifinition of basic gates

Redefinition of AND

Estimation functions

Estimations

Results Different selection group lengths with linearArray summation:

Results Wallace summation instead:

Results Different summation networks with simple PPG:

Results Regular summation networks: addTree carrySave

Limitations of the estimations Wiring delays Needs layout information Fan-out Several inputs connected to the same output  slower signal Only standard gates are used Better techniques exist for e.g full adders