1. ECE 352 Digital System Fundamentals
Re-Examining Carry Bit Calculation
In this presentation, we will take an in-depth look at the generation of carries in a binary adder. As we have seen previously in the ripple-carry adder, the carry-out from the least significant bit must propagate all the way through the adder to the most significant bit before the result is valid. This represents a significant delay.

2. Re-Examining Addition
For a bit position k, can the values of Ak and Bk tell us something about that position’s Cout before its Cin is known?
Specifically, can different combinations of Ak and Bk values guarantee that:
Cout is 1 regardless of the value of Cin?
Cout will be equal to Cin?
Cout is 0 regardless of the value of Cin?
Instead, we want to know if the values of the two operands at a given bit index can tell us something about the carry out BEFORE the carry-in is actually known.
There are three situations that we’re interested in. First, are there combinations of the A and B bits where the carry-out will be 1 regardless of the value of the carry-in? Second, are there combinations of the A and B bits where the value of the carry-out will be the same as the carry-in? And finally, are there combinations of the A and B bits where the carry-out will be 0 regardless of the value of the carry-in?

3. Cout is 1 regardless of Cin
Generating Carries
What values of A and B guarantee that Cout is 1 regardless of the value of Cin? 1 1
If we examine the truth table of a full adder, we see that the carry-out is always 1 when A and B are both 1. So, when A and B are both 1, we know that the carry-out will be 1 regardless of the carry-in, and so we say that this adder will “generate” a carry.
This bit position generates a carry, independent of results at lower bit positions!
Cout is 1 regardless of Cin
if A = 1 and B = 1

4. Cout is equal to Cin if A ≠ B
Propagating Carries
What values of A and B guarantee Cout equals Cin?
Two situations: 1 1
In the middle four rows of the truth table, either A or B is 1, but not both. In these rows, the carry-out is always the same as the carry-in. So we say that the adder will “propagate” a carry, since a carry-in of 1 will cause a carry-out of 1.
This bit position propagates the incoming carry value to the next position!
Cout is equal to Cin if A ≠ B

5. Cout is equal to Cin if A ≠ B
Propagating Carries
These values of A and B also guarantee that a Cin value of 0 will cause Cout to be 0
Two situations: 1 1
This also means that a carry-in of 0 will cause a carry-out of 0. Effectively, the carry value from the position to the right is propagated through the adder to the position to the left.
This bit position propagates the incoming carry value (even when the carry is 0) to the next position!
Cout is equal to Cin if A ≠ B

6. Sometimes Cout Must Be Zero
What values of A and B guarantee that Cout is 0 regardless of the value of Cin?
Finally, if A and B are both 0, then the carry-out must be 0 as well. So, an adder with A=0 and B=0 will not generate a carry, nor will it propagate a carry – we know its carry-out must be 0.
This bit position neither generates nor propagates a carry!
Cout is 0 regardless of Cin
if A = 0 and B = 0

7. Alternate Equations for Carry Bits
Adder cell k generates a carry if Ak and Bk are both 1
Gk = Ak Bk
Gk is TRUE if adder cell k generates a carry
Adder cell k propagates the carry if either Ak or Bk are 1, but not both
Pk = Ak XOR Bk
Pk is TRUE if adder cell k propagates a carry
How do we know if Ck+1, the carry-out of position k, is 1?
Let’s use these ideas to rewrite the carry equation for a full adder.
We say that an adder cell generates a carry if A and B are both 1. So, for the k-th bit, we call the generate output G_k , and it is equal to A_k AND B_k. We say that an adder cell propagates a carry if either A or B are 1, but not both. So, the propagate output P_k is equal to A_k XOR B_k.
We can use the definitions of generate and propagate to write an alternate equation for the carry-out of a full adder. The carry in to the adder for bit position k+1 is connected to the carry out of the adder for bit position k. This adder’s carry-out will be 1 if bit k generates a carry, or it propagates a carry and its carry-in is 1.
propagates a carry
AND
its Cin is 1
Bit position k’s Cout is 1 if it…
generates a carry OR
Ck+1 = Gk +
PkCk

8. Reorganizing the Full Adder
Partial Full Adder (PFA) plus carry chain logic
PFA: a full adder without the carry chain logic
Carry chain: computes the carry values based on the generate (G) and propagate (P) signals from the PFA
Carry Chain
Next, let’s modify the full adder to use these new ideas of generate and propagate. We separate the carry logic from the sum logic, producing what is called a partial full adder, or PFA. The PFA does not produce a carry output; instead, it produces propagate and generate outputs based on the values of A and B. The actual carry values are computed in the carry chain based on those propagate and generate signals. Note that they are labeled P for “propagate” and G for “generate” – the labels have meaning.
PFA

9. Ripple-Carry Adder With PFAs
Can create ripple-carry adder (RCA) with PFAs
G: Generates a carry at this position
P: Propagates a carry through this position
Could optimize the carry-chain to reduce delay…
C2 = G1 + P1 C1
Just like we do with full adders, we can create a ripple-carry adder using PFAs and carry chain logic. Each PFA produces a propagate and a generate output, and the ripple-carry chain combines these to produce the carry-in to each PFA – except for the PFA at the least-significant bit, which receives its carry-in C_0 from the carry-in input to the whole ripple-carry adder.
At this point, we haven’t really done anything but redraw the full adder logic, but soon we’ll reorganize the carry chain to reduce the carry delay. For now, it’s important to understand the meaning of propagate and generate, and to recognize that there will be a carry-out from a bit position if that bit position GENERATES a carry, or if it PROPAGATES a carry-in that is 1.
G1 = A1 B1
P1 = A1 XOR B1

10. Delay in Logic Circuits
A gate’s output is not actually the result of its logic function until some time after the input(s) change
This is that gate’s “gate delay”
Each gate along a path from a circuit input to a circuit output adds to the delay of that path
i.e., the length of time it will take for the circuit output to become valid after that circuit input changes value
The path with the longest delay from ANY input to ANY output is called the “critical path”
The worst-case delay for any change on any input
Why are we worried about the delay of the carry logic in a ripple-carry adder? Ideally, the output of a combinational logic gate would change instantaneously in response to a change on one or more of its inputs. In reality, though, it takes time for the gate’s transistors to operate, so there is a delay between change on a gate’s input and the corresponding change at the output. It’s a very small delay, but in a complex logic circuit all the small delays add up.
As you would expect, the more gates that a signal goes through, the more delayed the end result is. In the case of the carry chain logic, each AND and OR gate adds more delay, so as we make the ripple-carry adder wider to process operands with more bits, that delay gets longer.
The output of a logic circuit isn’t known to be valid until the input signals have traveled down all paths from the inputs to every output. The path with the longest delay determines the overall delay of the circuit, so we call that the “critical path”. If we want a circuit to operate faster, we need to reduce the delay on the critical path. In a ripple-carry adder, it’s probably no surprise that the critical path turns out to be the carry chain logic.

11. Why Compute the Carry Differently?
Ripple carry adders are small and easy to create
Minimal logic, good tileable structure
But ripple carry adders are slow!
Design is limited by the delays in propagating carry through all of the bitwise additions
The sum at any given bit position requires the values A0, B0, and C0 to propagate all the way to that point
Could optimize the carry-chain to reduce delay…
Ripple-carry adders are easy to create, because we can replicate a full-adder circuit as many times as we need and connect them together. They are also small, because the multi-level carry chain logic reuses the carry calculation from all the previous bits to compute the carry for the next bit.
Unfortunately, as we showed, ripple-carry adders are also slow, and they get proportionally slower as we make them larger. The signals applied to the least significant bit have to propagate all the way down the carry chain to the most significant bit before the output is known to be valid. If we want to perform addition faster, we’ll need to reduce the delay of the carry chain.

12. ECE 352 Digital System Fundamentals
Re-Examining Carry Bit Calculation
In the next video, we’ll introduce the carry-lookahead adder, where the carry chain has been reorganized to create a much faster (but larger) adder.