Clock & Control Timing and Link 29 July 2008 Matt Warren Maurice Goodrick, Bart Hommels, Marc Kelly, ABSTRACT: A data acquisition system is described which will be used for the next generation of prototype calorimeters for the International Linear Collider and could also be used for the final system. The design is sufficiently generic such that it should have applications elsewhere, be they other ILC detectors or within High Energy Physics in general: e.g. this could be applied to LHC upgrade apparatus. The concept of moving towards a "backplaneless" readout is pursued. A strong under-pinning thread here is to attempt to make use of commercial components and identify any problems with this approach. Therefore the system should be easily upgradable, both in terms of ease of acquiring new components and competitive prices. The conceptual design, both hardware and software, of the data acquisition system for the ILC calorimeter will be discussed. Results and tests already done will then be shown indicating both the potential and limitations of the approach.

Matt Warren & Co. - C&C Timing & Link Timing Overview C+C provides a fast clock (CLOCK) Expected to be 50-100MHz, local or machine. CCC does NOT support varied delays on individual outputs. LDAs do not adjust individual link timings Presumed cables to all LDAs equal length in a timing domain. Hoped that DIFs can adjust own timing if really needed using FPGA resources. CCC card can adjust timing of synchro-signals wrt CLOCK BUNCH-CLOCK (slow clock) derived as CLOCK/n Produced by a counter on the DIF Start of train signal (TRAINSYNC) synchronises bunch-clocks on all DIFs. Requires fixed-latency signal – a SYNCCMD. SYNCCMD “qualifies” CLOCK edge 29 Jul 08 Matt Warren & Co. - C&C Timing & Link

Matt Warren & Co. - C&C Timing & Link CCC Link Interface CCC should connect to LDA, DIF and ODR using the ‘standard’ HDMI cabling and connectors and pinout (CLink) But only a subset of the signals/functions used. CCC can be used as a pseudo-LDA for stand-alone DIF testing A distinction is made between fast and fixed latency signals. Fast signaling is asynchronous and uses a dedicated line to transfer a pulse. No attempt is made to encode data. Fixed-latency signaling will not arrive fast, but will arrive a known latency after reception by CCC. HDMI Signals CLink Signal Direction Function Type CLOCK_L2D LDA→DIF Distributed DIF Clock STP DATA_L2D Data to DIF (mainly configuration) DATA_D2L DIF→LDA Data from DIF (mainly events) ASYNC_L2D Asynchronous trigger UTP* GEN_D2L General use * Twisted pair not guaranteed by HDMI specification but seen in commercial cables 29 Jul 08 Matt Warren & Co. - C&C Timing & Link

Matt Warren & Co. - C&C Timing & Link CCC Link Signals CCC HDMI Signals CLink Signal CCC Signal Function CLOCK_L2D CLOCK_OUT Clock DATA_L2D TRAINSYNC_OUT Trainsync signal output DATA_D2L Unused ASYNC_L2D ASYNC_OUT Asynchronous signal GEN_D2L GEN_IN General purpose CLOCK Machine clock (50-100MHz) TRAINSYNC_OUT Synchronisation of all the front-end slow clocks. An external signal will be synchronized to the clock and transmitted as a single clock-period wide pulse to the LDA. To allow communicating with a stand-alone DIF, the CCC board will can be configured to send the LDA 8b/10b serialised command for train-sync. ASYNC_OUT Transfer asynchronous triggers as fast as possible. GEN_IN General purpose signal for use in communicating with the CCC (and therefore run control) system. A hardware OR of these signals is available on the CCC. 29 Jul 08 Matt Warren & Co. - C&C Timing & Link

Matt Warren & Co. - C&C Timing & Link SYNCCMD Details SYNCCMD is the ONLY mechanism for synchronising DIFs 4 types of command are possible, but only one is required. Expects a PRE bunch-train/spill signal Signal in known phase with BUNCH CLOCK Hopefully PRE-signal is a fixed period prior to first bunch of train Synchronous to CLOCK CCC card forwards signal to LDAs Synchronises signal to local clock when needed LDA stores arrival time wrt serialised bit number. Next Word to DIFs replaced with special SYNCCMD word First byte dedicated K character Second byte (7:6): Type; (5:0): Delay (could be 3:5 ratio too) SYNCCMD system on DIF delays signal specified number of CLOCKs and issues the required signal. Data 15:8 Data 7:0 KSYNCCMD 0:8 Data 15:8 Data 7:0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LDA In DIF Out 29 Jul 08 Matt Warren & Co. - C&C Timing & Link