PC Buses & Standards Bus = Pathway across which data can travel. Can be established between two or more computer elements. PC has a hierarchy of different buses (each slower bus is connected to a faster one above it) Each device in a system is connected to one of the buses. Some devices (primarily chipsets) act as bridges between the various buses. 10/04/2002 ET4508_p (KR)

PC Buses & Standards Main buses in a modern system: Processor Bus Also called front-side bus (FSB). Highest-speed bus in the system. Primarily used by between processor, memory, and chipset. PCI Bus State-of-the-art I/O Bus AGP Bus High-speed video bus ISA Bus Legacy I/O Bus Various internal Buses LPC, AHA 10/04/2002 ET4508_p (KR)

PC Buses & Standards PC Buses are physically implemented as Tracks on a PCB or as signals on a connector PC Buses comprise the following: Address Bus Data Bus Control Bus 10/04/2002 ET4508_p (KR)

Example: Socket-7 System 10/04/2002 ET4508_p (KR)

PC Buses & Standards First bus connects the CPU with RAM Modern PCs call this the Host Bus Speed & Width depend on the CPU & the RAM type – typically 64-bits & 66-133MHz Expansion buses are a lot slower than the Host Bus 10/04/2002 ET4508_p (KR)

PC/AT Diagram 10/04/2002 ET4508_p (KR)

Modern PC Architecture 10/04/2002 ET4508_p (KR)

PC/AT Architecture: Reference 1987: Compaq decoupled the CPU bus from other buses – now the norm 10/04/2002 ET4508_p (KR)

Common PC Buses ISA Bus Older low speed bus – now being phased out of PC designs EISA An improved version of the ISA bus PCI Bus Newer high speed bus – bus of choice for new expansion devices USB Bus A serial bus (now supporting high speeds), targeted at external hardware, eg keyboards and other peripherals FireWire (IEEE 1394) A high speed bus, targeted at external devices that need high data rates, e.g. video. AGP Bus Accelerated Graphics Port - an advanced graphics bus 10/04/2002 ET4508_p (KR)

PC Buses: MicroChannel Released by IBM in 1987 Technically excellent but proprietary solution hence did not take off MCA bus: 32 bit wide and "intelligent" Cards configure themselves so they can be installed without jumper switches MCA works at 10.33 MHz, asynchronous to the system bus Not Compatible with ISA boards 10/04/2002 ET4508_p (KR)

PC Buses: EISA EISA: Extended Industry Standard Architecture Developed by Gang of Nine as competitor to MCA 10/04/2002 ET4508_p (KR)

EISA Key Features ISA Add-in cards can be plugged into the EISA Bus slots imposed a design restriction on the EISA standard 8.33MHz bus clock (for ISA support) 16- or 32-bit data transfers (ISA is 8- or 16-bit) Adapter card pulls EX32 or EX16 for card width Faster DMA Supports i386/i486 faster bus timing Level triggered interrupts Switch-free software setup (a big advantage) 10/04/2002 ET4508_p (KR)

EISA Block Diagram 10/04/2002 ET4508_p (KR)

EISA Bus Control and Timing EISA: synchronised bus BCLK is derived from the processor clock The EISA Bus Controller distinguishes between EISA and ISA bus cycles and executes EISA bus cycles in various modes Bus Controller supplies EISA/ISA Bus Control signals Some EISA boards have their own Bus Master – they can take over the EISA Bus 10/04/2002 ET4508_p (KR)

EISA Bus Control and Timing (2) BCLK is derived from the processor clock: Max freq = 8.33MHz EISA bus cycles in various modes Standard: i386 type 8.33MHz (2 x CLK periods) Burst: i486 type BCLK stretching for slower devices EMB-66 (32-bits) & EMB-133 (64-bits) use both edges of the BCLK for transfer 8.33MHz x 2 = 16.66MHz 4 bytes @ 16.66MHz => 66MByte/s 10/04/2002 ET4508_p (KR)

Bus Arbitration Logic – Bus Mastering ISA Crude and Simplistic type bus mastering by a device other than the CPU, i.e. DMA – no arbitration logic EISA Much more sophisticated arbitration scheme – bus mastering allows other devices to take over the bus – supports multiprocessing as well.  e.g. other CPU, LAN controller Levels of Arbitration DMA and DRAM Refresh – HIGHEST PRIORITY CPU Other devices - LOWEST PRIORITY   EISA Bus can include several masters at any level (rotating priority). MREQ initiates a request for the EISA Bus. EISA bus masters don’t have to handle refresh – unlike AT 10/04/2002 ET4508_p (KR)

EISA Bus DMA Full 32-bit address available for DMA Transfers DMA Modes Compatible Mode (ISA bus i8237A type timing) A: 6 x BCLKs (improved memory phase, same I/O timing) Most ISA cards will run in this mode B: 4 x BCLKs (improved Memory and I/O phase) Some later ISA cards can take advantage of this C: EISA Devices, which support Burst cycles ONE DMA transfer in 1 BCLK 10/04/2002 ET4508_p (KR)

EISA Bus DMA (2) 2 DMA Page Registers Low Page – same as conventional DMA Page register High Page - high order address byte A24-A31 Rotating DMA priority – one device cannot hog the bus  7 DMA channels - can be assigned as in the PC/AT As usual DMA Control registers are I/O Mapped 10/04/2002 ET4508_p (KR)

EISA Interrupt Controller 15 interrupt levels assigned as in the PC/AT Level Triggered – allows several devices to share an IRQ can be configured for edge trigger operation Edge Triggered – AT style (ISA bus) 10/04/2002 ET4508_p (KR)

Connectors: ISA vs EISA 10/04/2002 ET4508_p (KR)

Local Buses: VL-Bus EISA offered performance improvements but was still a bottleneck with high performance peripherals. E.g. Network Interface Cards Disk Controllers Video Adapters For higher performance systems try to connect fast peripheral devices direct to the CPU Bus – i.e. the Local Bus BUT these connections can cause bus-loading and timing problems 10/04/2002 ET4508_p (KR)

Local Bus Standards VESA VL-Bus PCI Bus (Intel) AGP (Accelerated Graphics Port) 10/04/2002 ET4508_p (KR)

VESA Local Bus Originally a 32-bit bus, but has been updated for 64-bit data. Sixteen bit data transfers are also supported. Up to three VL-Bus devices can be inserted into the VL-Bus physical slots. MCA-type connector provides the local bus signals. Note that the full bus is realised in conjunction with an ISA or EISA slot 10/04/2002 ET4508_p (KR)

VESA Local Bus Max Clock Rate: 66MHz: if all VL-Bus devices are integrated on the Motherboard 40MHz: if external connector slots are used VL-Bus devices are defined as LBM or LBT LBM: Local Bus Master – can take full control of the bus at any time LBT: Local Bus Target – driven by the VL-Bus to transfer data VL-Bus Controller logic implements the necessary bus arbitration 10/04/2002 ET4508_p (KR)

VL-Bus Connector 10/04/2002 ET4508_p (KR)

VL-Bus Block Diagram

VL-Bus Limitations The VL-Bus design is almost a copy of the i486 bus. A disadvantage for the following reasons: It was not easy to modify for the Pentium Bus VL-Bus is not an independent bus, which can be designed into other microprocessor-based systems Intel wanted a local bus which was decoupled from the actual processor bus, and which could also be used with ‘foreign’ microprocessors Intel developed the PCI-bus to displace the VL-Bus. 10/04/2002 ET4508_p (KR)