CSE 370 – Winter 2002 - Sequential Logic-2 - 1 Overview Last lecture Timing methodologies Registers Today Counters (a first view) Finite state machines 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 1

CSE 370 – Winter 2002 - Sequential Logic-2 - 2 Pattern recognizer Combinational function of input samples in this case, recognizing the pattern 1001 on the single input signal D Q IN OUT1 OUT2 OUT3 OUT4 CLK OUT 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 2

CSE 370 – Winter 2002 - Sequential Logic-2 - 3 Counters Sequences through a fixed set of patterns in this case, 1000, 0100, 0010, 0001 if one of the patterns is its initial state (by loading or set/reset) Mobius (or Johnson) counter in this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 D Q IN OUT1 OUT2 OUT3 OUT4 CLK D Q IN OUT1 OUT2 OUT3 OUT4 CLK 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 3

CSE 370 – Winter 2002 - Sequential Logic-2 - 4 Binary counter Logic between registers (not just multiplexer) XOR decides when bit should be toggled always for low-order bit, only when first bit is true for second bit, and so on D Q OUT1 OUT2 OUT3 OUT4 CLK "1" 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 4

Four-bit binary synchronous up-counter Standard component with many applications positive edge-triggered FFs w/ synchronous load and clear inputs parallel load data from D, C, B, A enable inputs: must be asserted to enable counting RCO: ripple-carry out used for cascading counters high when counter is in its highest state 1111 implemented using an AND gate EN D C B A LOAD CLK CLR RCO QD QC QB QA (2) RCO goes high (3) High order 4-bits are incremented (1) Low order 4-bits = 1111 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 5

CSE 370 – Winter 2002 - Sequential Logic-2 - 6 Offset counters Starting offset counters – use of synchronous load e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . . Ending offset counter – comparator for ending value e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000 Combinations of the above (start and stop value) "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "1" "1" "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "0" "0" "0" 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 6

Sequential logic summary Fundamental building block of circuits with state latch and flip-flop R-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop Timing methodologies use of clocks cascaded FFs work because propagation delays exceed hold times beware of clock skew Asynchronous inputs and their dangers synchronizer failure: what it is and how to minimize its impact Basic registers shift registers pattern detectors counters 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 7

Sequential logic implementation Sequential circuits primitive sequential elements combinational logic Models for representing sequential circuits finite-state machines (Moore and Mealy) representation of memory (states) changes in state (transitions) Basic sequential circuits shift registers counters Design procedure state diagrams state transition table next state functions 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 8

Abstraction for a state machine Divide circuit into combinational logic and state Localize the feedback loops and make it easy to break cycles Implementation of storage elements (e.g., D flip-flops, T flip-flops) alter the logic Combinational Logic Storage Elements Outputs State Outputs State Inputs Inputs 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 9

Forms of sequential logic Asynchronous sequential logic – state changes occur whenever state inputs change (feedback elements may be wires or delay elements) Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Clock Asynchronous Synchronous 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 10

Finite state machine representations States: determined by possible values in sequential storage elements Transitions: change of state Clock: controls when state can change by controlling storage elements Sequential logic sequences through a series of states based on sequence of values on input signals clock period defines elements of sequence In = 0 In = 1 100 010 110 111 001 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 11

Example finite state machine diagram Combination lock from introduction to course reset S3 closed mux=C1 equal & new not equal & new not new S1 S2 OPEN ERR mux=C2 mux=C3 open 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 12

Representing sequential system using state diagrams Shift register input value shown on transition arcs output values shown within state node D Q IN OUT1 OUT2 OUT3 CLK 1 100 110 111 011 101 010 000 001 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 13

Counters are simple(st) finite state machines proceed through well-defined sequence of states in response to enable No input Many types of counters: binary, BCD, Gray-code 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... 010 100 110 011 001 000 101 111 3-bit up-counter 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 14

How do we turn a state diagram into logic? Counter 3 flip-flops to hold state (8 states; 1 FF per bit) logic to compute next state clock signal controls when flip-flop memory can change wait long enough for combinational logic to compute new value don't wait too long as that is low performance D Q OUT1 OUT2 OUT3 CLK "1" 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 15

CSE 370 – Winter 2002 - Sequential Logic-2 - 16 FSM design procedure Start with counters simple because output is just state simple because no choice of next state based on input State diagram to state transition table tabular form of state diagram like a truth-table State encoding decide on representation of states for counters it is simple: just its value Implementation flip-flop for each state bit combinational logic based on encoding 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 16

FSM design procedure: state diagram to encoded state transition table Tabular form of state diagram Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters – just use value current state next state 0 000 001 1 1 001 010 2 2 010 011 3 3 011 100 4 4 100 101 5 5 101 110 6 6 110 111 7 7 111 000 0 010 100 110 011 001 000 101 111 3-bit up-counter 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 17

CSE 370 – Winter 2002 - Sequential Logic-2 - 18 Implementation D flip-flop for each state bit Combinational logic based on encoding notation to show function represent input to D-FF C3 C2 C1 N3 N2 N1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 N1 := C1' N2 := C1C2' + C1'C2 := C1 xor C2 N3 := C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 0 0 0 1 1 1 C1 C2 C3 N3 0 1 1 0 C1 C2 C3 N2 1 1 0 0 C1 C2 C3 N1 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 18

Implementation (cont'd) Programmable logic building block for sequential logic macro-cell: FF + logic D-FF two-level logic capability like PAL (e.g., 8 product terms) D Q Q 1/2/2019 CSE 370 – Winter 2002 - Sequential Logic-2 - 19