Copyright © 2010 Agilent Technologies Characterizing the Physical Layer of MIL-STD 1553 Differential Bus Networks Presented by: Johnnie Hancock Agilent.

Slides:



Advertisements
Similar presentations
Chapter 14 Communications Introduction
Advertisements

Using Matrices in Real Life
Chapter 1 The Study of Body Function Image PowerPoint
1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 4 Computing Platforms.
1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 1 Embedded Computing.
OSPF 1.
Summary of Second Draft of the NERC Standard PRC Disturbance Monitoring and Reporting JSIS Meeting August 10, 2010 Salt Lake City, UT.
How Much Do I Remember? Are you ready to play.....
Environmental Remote Sensing GEOG 2021
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
Integrify 5.0 Tutorial : Creating a New Process
Filters and Enveloping - A Practical Discussion -
JAZiO Incorporated 1 Change No-Change Concept. JAZiO Incorporated 2 Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is.
Bus arbitration Processor and DMA controllers both need to initiate data transfers on the bus and access main memory. The device that is allowed to initiate.
MIL/STD-1553B Bus Overview J. Frederick Bartlett Fermilab June 3, 1999.
Processor Data Path and Control Diana Palsetia UPenn
Mehdi Naghavi Spring 1386 Operating Systems Mehdi Naghavi Spring 1386.
Suite Suite 2 TPF Software – Overview Binary Editor Remote Scripts zTREX Add-Ins & Project Integration with Source Control Manager.
Beckett Energy Systems
Introduction to DDR SDRAM
1 Chapter Overview Network Cables Network Interface Adapters Network Hubs.
Microsoft Access.
Chapter 3 Basic Logic Gates 1.
1 1 Mechanical Design and Production Dept, Faculty of Engineering, Zagazig University, Egypt. Mechanical Design and Production Dept, Faculty of Engineering,
Chapter 4 Gates and Circuits.
Chapter 3 (part 1) Basic Logic Gates 1.
Flip-Flops and Registers
Chapter 15 Integrated Services Digital Network ISDN Services History Subscriber Access Layers BISDN WCB/McGraw-Hill The McGraw-Hill Companies, Inc., 1998.
Exercise 1: Install PC Software & NXT Firmware
DAQmx下多點(Multi-channels)訊號量測
Chapter 4 Gates and Circuits.
 Copyright I/O International, 2013 Visit us at: A Feature Within from Item Class User Friendly Maintenance  Copyright.
Chapter 5 Microsoft Excel 2007 Window
© 2007 Cisco Systems, Inc. All rights reserved.Cisco Public 1 EN0129 PC AND NETWORK TECHNOLOGY I IP ADDRESSING AND SUBNETS Derived From CCNA Network Fundamentals.
Chapter 10 Software Testing
Executional Architecture
Global Analysis and Distributed Systems Software Architecture Lecture # 5-6.
25 seconds left…...
Equal or Not. Equal or Not
Slippery Slope
Gursharan Singh Tatla PIN DIAGRAM OF 8086 Gursharan Singh Tatla Gursharan Singh Tatla
Chapter 10: The Traditional Approach to Design
Systems Analysis and Design in a Changing World, Fifth Edition
We will resume in: 25 Minutes.
© 2007 Cisco Systems, Inc. All rights reserved.Cisco Public 1 Addressing the Network – IPv4 Network Fundamentals – Chapter 6.
©2004 Brooks/Cole FIGURES FOR CHAPTER 12 REGISTERS AND COUNTERS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.
Connecting LANs, Backbone Networks, and Virtual LANs
Practical Considerations for Digital Design
©2004 Brooks/Cole FIGURES FOR CHAPTER 11 LATCHES AND FLIP-FLOPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.
Chapter 13 Shift Registers
Nokia 30 technical specification
T.30 Overview APAC FAE Training
Installing Windows XP Professional Using Attended Installation Slide 1 of 30Session 8 Ver. 1.0 CompTIA A+ Certification: A Comprehensive Approach for all.
McGraw-Hill©The McGraw-Hill Companies, Inc., 2001 Chapter 16 Integrated Services Digital Network (ISDN)
User Friendly Item Relationship Maintenance A Family of Enhancements For iSeries 400 DMAS from  Copyright I/O International, 2006, 2007, 2008, 2010 Skip.
ECE 424 – Introduction to VLSI
THS3000 Product Introduction Market Dynamics  Customers require more flexible solutions  Many test solutions are driven by both measurement needs.
Figure 1–1 Graph of an analog quantity (temperature versus time). Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper.
MICE III 68000/20/30 MICETEK International Inc. CPU MICEIII MICEView Examples Contents Part 1: An introduction to the MC68000,MC68020 and Part.
High Speed Memory Debug Techniques presented by: Jennie Grosslight Project Development Manager Memory Solutions FuturePlus ® Systems Corporation.
TLA5000B Series Logic Analyzer Fact Sheet Breakthrough solutions for real-time digital systems analysis Featuring:  125 ps-resolution MagniVu™ acquisition.
WaveSurfer 3000 Oscilloscopes Public Release – July 1 st, 2014.
FeaturesBenefits MagniVu™ acquisitionAvoid missing events completely in either timing or state acquisition mode with higher sampling resolution (up to.
NSBE Seminar1 MIL-STD 1553 on the International Space Station’s Command and Data Handling System NSBE training seminar September 25, 2003 P.Eugene Jackson.
Crashcourse Oscilloscope and Logic Analyzer By Christoph Zimmermann.
Generic Remote Interface Unit (RIU) Interface Control Document (ICD)
Presentation transcript:

Copyright © 2010 Agilent Technologies Characterizing the Physical Layer of MIL-STD 1553 Differential Bus Networks Presented by: Johnnie Hancock Agilent Technologies

Copyright © 2010 Agilent Technologies 2 Objectives Learn how to quickly verify the electrical/physical layer input and output characteristics of MIL-STD 1553 differential serial buses using a Digital Storage Oscilloscope (DSO) with MIL-STD 1553 bus decoding and triggering capability. Learn how eye-diagram mask testing can provide a composite measure of the signal integrity of your MIL-STD 1553 differential bus.

Copyright © 2010 Agilent Technologies 3 Agenda MIL-STD 1553 Protocol & Timing Overview MIL-STD 1553 Electrical/Physical Layer Requirements Triggering and Decoding MIL-STD 1553 Serial Buses Isolating Physical Layer Measurements on Remote Terminal (RT) and Bus Controller (BC) generated Signals MIL-STD 1553 Eye-diagram Mask Testing Clock Recovery Technique

Copyright © 2010 Agilent Technologies 4 MIL-STD 1553 Protocol & Timing Overview Word Length = 20 bits (3-bit Sync field, 16-bit content field, 1-bit parity field) Word Types: Command (Packets transmitted by BCs) Status (Packets transmitted by RTs) Data (Packets transmitted by BCs and RTs) Baud Rate = 1 Mb/s Encoding = Manchester II Bi-phase (except 3-bit Sync field)

Copyright © 2010 Agilent Technologies 5 Manchester II Bi-phase Encoding NRZ Encoding High during middle of bit time = 1 Low during middle of bit time = 0 Manchester II Bi-phase Encoding High to low transition in middle of bit time = 1 Low to high transition in middle of bit time = 0

Copyright © 2010 Agilent Technologies 6 Message Formats Message Formats (Master/Slave Relationship) Example #1: BC to RT Transfers (BC sends data to RT) Note: Signals probed at BC input/output test plane A Packet - Command Word from BC to RTA = 0F w/ receive bit set: Get ready accept data. A A B Packets - 5 Data Words transmitted from BC to RT BBBBB BBB C Packet - Status Word from RTA = 0F: Got it! C C

Copyright © 2010 Agilent Technologies 7 Message Formats Message Formats (Master/Slave Relationship) Example #2: RT to BC Transfers (BC requests data from RT) Note: Signals probed at RT input/output test plane A Packet - Command Word from BC to RTA = 02 w/ transmit bit set: Send me data. A A B Packet - Status Word from RTA = 02: Here it comes! B B C Packets - 4 Data Words transmitted from RT to BC CCCC CCC

Copyright © 2010 Agilent Technologies 8 Message Formats Message Formats (Master/Slave Relationship) Example #3: RT to RT Transfers (BC requests RT 2 to send data to RT 1) Scope waveforms not available A Packet - Command Word from BC to RTA 1 w/ receive bit set: Get ready accept data. A A B Packet – Command Word from BC to RTA 2 w/ transmit bit set: Send data to RT 2. B B C Packet – Status Word from RTA 2: Here it comes! C C E E Packet – Status Word from RTA 1: Got it! E DDD D Packets - N Data Words transmitted from RT 2 to RT 1 DDDD Note: Signals probed at RT2 input/output test plane

Copyright © 2010 Agilent Technologies 9 Primary Electrical/Physical Layer Specifications Transformer CoupledDirect Coupled Terminal Output Specs Voltage Swing18 to 27 V p-p6 to 9 V p-p Overshoot 900 mV 300 mV Noise 14 mV RMS 5 mV RMS Transition Time100 to 300 ns (10/90) Zero Crossing Distortion 25 ns Output Symmetry< 250 mV< 90 mV Terminal Input Specs Voltage Swing0.86 to 14 V p-p1.2 to 20 V p-p Input Rejection V 0.2 V 0.28 V Zero Crossing Distortion 150 ns Other Important Timing Parameters Intermessage Gap: 4 µs (parity bit crossing to next sync edge) Response Time: 4 to 12 µs (parity bit crossing to next sync edge)

Copyright © 2010 Agilent Technologies 10 Measurement Test Planes Data Device Corporation Graphic All terminals are transceivers. Both output/transmitted and input/received signals are present at all differential terminal I/O pins. Making oscilloscope parametric and timing measurements on specific transmitted or received words can be enhanced with intelligent oscilloscope triggering.

Copyright © 2010 Agilent Technologies 11 The Problem: Most of todays scopes trigger on simple edge crossing conditions Simple edge triggering cant differentiate between transmitted and received words. External/synchronization signals are rarely available. Resultant measurements and display are composites of ALL words.

Copyright © 2010 Agilent Technologies 12 Required MIL-STD 1553 Triggering Input Measurements Received signals at BC transmitted from RT1 Probe at BC Trigger on Status Words from RTA = 1 Output Measurements Transmitted signals at BC Probe at BC Trigger on Command Words Received signals at RT1 transmitted from BC Probe at RT1 Trigger on Command Words Received signals at RT2 transmitted from RT3 Probe at RT2 Trigger on Status Words with RTA = 3 Transmitted signals at RT1 Probe at RT1 Trigger on Status Words from RTA = 1 Transmitted signals at RT2 Probe at RT2 Trigger on Status Words with RTA = 2 Transmitted signals at RT3 Probe at RT3 Trigger on Status Words with RTA = 3 Note 1: Bus Monitor (protocol analyzer) 1

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Triggering options: Data Word Start Data Word Stop Command/Status Word Start Command/Status Word Stop Remote Terminal Address RTA + 11 Bits Parity Error Sync Error Manchester Error Triggering on MIL-STD 1553 Signals Note: The RTA + 11 bits trigger mode can be used to trigger on and differentiate between specific Command and Status Words.

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Sub-address = 30 (decimal) Command versus Status Word Triggering Command Word Trigger Status Word Trigger Trigger: RTA + 11 bits = 02 HEX XXXXX Using the RTA + 11 bits Trigger Mode Trigger: RTA + 11 bits = 02 HEX + X 0X000 XXXXX Command Word Status Word Status bits Trigger Command Word Status Word

Copyright © 2010 Agilent Technologies 15 Measuring received signals at RT2 transmitted by the BC Rise Time & V RT input MIL-STD 1553 Trigger Setup (Command Word Trigger: RTA = 2, Transmit, Sub = 1110) T/R Sub-Address Command Word received from BC

Copyright © 2010 Agilent Technologies 16 Measuring received signals at RT2 transmitted by the BC MIL-STD 1553 Trigger Setup (Command Word Trigger: RTA = 2, Transmit, Sub = 1110) T/R Sub-Address Response Time

Copyright © 2010 Agilent Technologies 17 Measuring received signals at RT2 transmitted by the BC Intermessage Gap Time MIL-STD 1553 Trigger Setup (Command Word Trigger: RTA = 2, Transmit, Sub = 1110) T/R Sub-Address Intermessage Gap

Copyright © 2010 Agilent Technologies November 2007 Page 18 Vertically closing eye due to noise and/or insufficient signal level Horizontally closing eye due to jitter and/or signal timing errors Eye-diagrams display worst-case jitter, vertical noise, & signal anomalies. Conventional eye-diagrams measurements require a reference clock signal for triggering. MIL-STD 1553 signals dont supply an explicit reference clock signal. Generating MIL-STD eye-diagram measurements requires either a software- or hardware-recovered clock. MIL-STD 1553 Eye-diagram Mask Testing Eye-diagram measurements provide a composite measure of overall system signal integrity by overlaying all bits of each word.

Copyright © 2010 Agilent Technologies November 2007 Page 19 1.Scope triggers on specific word in order to capture and display input or output signals at a particular test plane. 2.Scopes timebase is scaled to repetitively capture just the 1 st Manchester-encoded bit (bit #4) for 50 milliseconds with infinite-persistence turned on. 3.Scopes timebase is scaled to repetitively capture just the 2 nd Manchester-encoded bit (bit #5) for 50 milliseconds with infinite-persistence turned on. 4.Scope steps through and repetitively captures all 17 Manchester-encoded bits (bits 4 through 20) for 50 milliseconds each with infinite persistence turned on, and then repeats. MIL-STD 1553 Hardware Clock Recovery Algorithm Note: This is an automated test sequence that runs within the scope when a MIL-STD 1553 mask test file is recalled.

Copyright © 2010 Agilent Technologies November 2007 Page 20 Building the MIL-STD 1553 Eye Bit #4Bit #5Bit #6Bit #7Bit #8Bit #9 Bit #4 Bit #5Bit #6 Bit #7 Bit #8Bit #9 … Sync Field = Bits … Bits

Copyright © 2010 Agilent Technologies November 2007 Page 21 With Manchester encoding, the MIL-Std 1553 eye-diagram measurement consists of 2 eyes/bit. Signal transitions should always occur near mid-point of each bit time. Signal transitions may or may not occur near bit time boundaries. The diamond-shaped pass/fail mask is based on the voltage swing (0.86 V p-p for xformer input test plane) and zero-crossing-distortion (+/- 150 input test plane) specifications. The MIL-STD 1553 Double Eye

Copyright © 2010 Agilent Technologies November 2007 Page 22 The electrical/physical layer of MIL-STD 1553 networks should be characterized to insure good signal integrity for reliable communication. Using an oscilloscope with built-in MIL-STD 1553 triggering and decoding will enhance your ability to quickly window-in on specific transmitted and received words for physical layer characterization. MIL-STD 1553 eye-diagram mask testing provides a composite measure of your systems physical layer characteristics. Summary

Copyright © 2010 Agilent Technologies Page 23 Agilents InfiniiVision Series Oscilloscopes SeriesBandwidthSample Rate (Max) Memory Depth MSODisplaySeg Mem Battery Option 7000B100 MHz to 1 GHz4 GSa/s8MYes 12.1 XGA YesNo 6000A100 MHz to 1 GHz4 GSa/s8MYes6.3 XGAYes 6000L100 MHz to 1 GHz4 GSa/s8MYesNoneYesNo 5000A 100 MHz to 500 MHz 2 GSa/s8MNo6.3 XGAYesNo MSO/DSO7000B MSO/DSO6000A DSO5000AMSO/DSO6000L Engineered for Best Signal Visibility Option 553: MIL-STD 1553 Trigger & Decode Option LMT: Mask Testing N2791A: 25-MHz Differential Active Probe

Copyright © 2010 Agilent Technologies Page 24 Application-specific Measurement Options for InfiniiVision Series Oscilloscopes MeasurementFactory-installed OptionAfter-purchase Upgrade MIL-STD 1553Option 553N5469A I 2 C/SPIOption LSSN5423A RS-232/UARTOption 232N5457A CAN/LINOption AMSN5424A FlexRayOption FLXN5432C I2SI2SOption SNDN5468A Mask TestOption LMTN5455A Segmented MemoryOption SGMN5454A

Copyright © 2010 Agilent Technologies November 2007 Page 25 Characterizing the Physical Layer of MIL-STD 1553 Differential Bus Networks

Copyright © 2010 Agilent Technologies November 2007 Page 26

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Agilents InfiniiVision Series Oscilloscopes for MIL-STD 1553 Testing (Option ) Compatible models: All 5000, 6000, and 7000 series 4-channel DSOs and 4+16 channel MSOs Industrys only hardware-based decode enhances probability of capturing MIL-STD 1553 communication errors Flexible MIL-STD 1553 triggering modes Automatic Search & Navigation (7000B only) Optional battery operation (6000A series only) MIL-STD 1553 eye-diagram mask testing (requires Option LMT 2 ) Entry-level Price: DSO5014A - $5300 Option $1300 Option LMT 2 - $ 700 N2791A Diff Probe -$ 600 Total System Price - $7900 Notes: 1.For after-purchase upgrade on an existing oscilloscope order N5469A. 2.For after-purchase upgrade on an existing oscilloscope order N5455A.

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Decode Display: Lister table Time-aligned trace Numeric/Symbol Format: HEX Binary Basic Word-type Symbol Word Type: Cmd/Status (green) Data (white) Bits: Remote Terminal Address (green) Command/Status Bits 9-19 (green) 16 Bits of Data Word (white) Errors Parity (red) Sync (red) Manchester (red) Decode Lister Time-aligned Decode Trace Decoding the MIL-STD 1553 Bus

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 RTA Word Type 11 Bits16 Bits Word Type Command/Status Word Sync Data Word Sync Time-Aligned Decode Trace HEX Decode Binary Decode

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Triggering options: Data Word Start Data Word Stop Command/Status Word Start Command/Status Word Stop Remote Terminal Address RTA + 11 Bits Parity Error Sync Error Manchester Error Triggering on MIL-STD 1553 Signals Note: The RTA + 11 bits trigger mode can be used to trigger on and differentiate between specific Command and Status Words.

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Sub-address = 30 (decimal) Command versus Status Word Triggering Command Word Trigger Status Word Trigger Trigger: RTA + 11 bits = 02 HEX XXXXX Using the RTA + 11 bits Trigger Mode Trigger: RTA + 11 bits = 02 HEX Command Word Status Word Status bits Trigger Command Word Status Word

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Error Analysis and Triggering Parity Error Sync Error Manchester Encoding Error Manchester Encoding Error = Missing transition within bit time

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 Automatic Search & Navigation

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 MIL-STD 1553 Mask Test Files Free downloadable mask files: System xfmr-coupled Input.msk System direct-coupled Input.msk BC to RT xfmr-coupled Input.msk BC to RT direct-coupled Input.msk RT to BC xfmr-coupled Input.msk RT to BC direct-coupled Input.msk RT to RT xfmr-coupled Input.msk RT to RT direct-couple Input.msk MIL-STD 1553 eye-diagram mask test files can downloaded at:

Copyright © 2010 Agilent Technologies MIL-STD 1553 Option August 2009 The MIL-STD 1553 differential bus must be probed with a differential active probe. Output of differential probe must be fed into two channels of the scope in order to establish dual threshold triggering (upper and lower thresholds). Probe Output Agilents N2791A 25-MHz differential active probe is recommended (US$600). Probing a MIL-STD 1553 Differential Bus