1 Pixel Bus Development Atsushi Taketani RIKEN/RBRC 1.Who is working 2.Over view of pixel bus 3. Manufacture process 4. Issues 5. Development / Production.

Slides:

Advertisements

Similar presentations

Silicon Technical Specifications Review General Properties Geometrical Specifications Technology Specifications –Mask –Test Structures –Mechanical –Electrical.

Advertisements

Year 6/7 mental test 5 second questions

1 New build-up technique with copper bump AGP Process.

Hybrid pixel: pilot and bus K. Tanida (RIKEN) 06/09/03 Si upgrade workshop Outline Overview on ALICE pilot and bus Requirements Pilot options Bus options.

Nose Cone Calorimeter sampling layers 2.5 mm. NCC EM bricks Had bricks.

EELE 461/561 – Digital System Design

ITS-week CERN December 3, 2001 Michel Morel CERN EP/ED.

Cosmic Ray Test of GEM- MPI/TPC in Magnetic Field Hiroshima University Kuroiwa CDC Group Mar

Detector module development for the CBM Silicon Tracking System Anton Lymanets for the CBM collaboration Universität Tübingen, Kiev Institute for Nuclear.

Module design for B-layer replacement V.1. Bare Module dimensions mm Active area mm mm Footprint mm stack 200um chip 20um bumps.

5.9 + = 10 a)3.6 b)4.1 c)5.3 Question 1: Good Answer!! Well Done!! = 10 Question 1:

Number bonds to 10,

Present Assembly Status Three important milestones completed: – We tried the entire assembly procedure on real modules and it worked – The construction.

ASE Flip-Chip Build-up Substrate Design Rules

General needs at CERN for special PCB’s Philippe Farthouat CERN.

Brenna Flaugher Oct. 31 th CDF Meeting1 RunIIb Silicon Project Successful Lehman Review Sept Workshop at LBL 10/23-10/25: Wednesday-Thursday  hybrids.

Operational prototype work at CERN Status report MM Gen. Meeting, 06/11/2013 J. Wotschack1.

1 CARRIER BUS LAYOUT(a) ± 193 mm ladder1ladder mm mm Pixel chip Michel Morel EP/ED 09/ x 425µ 256 x 50µ Decoupling capacitors

Read-out boards Rui de Oliveira 16/02/2009 RD51 WG1 workshop Geneva.

WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status.

1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki

1 CARRIER BUS LAYOUT(a) ± 193 mm ladder1ladder mm mm Pixel chip Michel Morel EP/ED 09/ x 425µ 256 x 50µ Decoupling capacitors

SVX4 chip 4 SVX4 chips hybrid 4 chips hybridSilicon sensors Front side Back side Hybrid data with calibration charge injection for some channels IEEE Nuclear.

Avogadro-Scale Engineering: Form and Function MIT, November 18, Three Dimensional Integrated Circuits C.S. Tan, A. Fan, K.N. Chen, S. Das, N.

V. Cindro, Jožef Stefan Institute, Ljubljana, Slovenia SCT week, Valencia, June 2002 Pre-series Low Mass Tapes 12 different lengths were produced for barrel.

PHENIX Silicon Pixel Detector Construction, Operation, and the first Results Atsushi Taketani RIKEN Nishina center RIKEN Brookhaven Research Center Outline.

1 Module and stave interconnect Rev. sept. 29/08.

Multilayer thin film technology for the STS electronic high density interconnection E. Atkin Moscow Engineering Physics Institute (State University) –

1 The 3-rd Work Meeting of the CBM -MPD STS Consortium “Technical challenges of the CBM and MPD Silicon Tracking Systems 2009” THE CABLES FOR THE CABLES.

1 Physics of Compressed Baryonic Matter 12 th CBM Collaboration Meeting R&D ON MICRO-CABLES FOR BABY SENSOR RADIATION TEST MODULE October , 2008.

Pixel hybrid status & issues Outline Pixel hybrid overview ALICE1 readout chip Readout options at PHENIX Other issues Plans and activities K. Tanida (RIKEN)

Frontend of PHENIX Si pixel K. Tanida (RIKEN) FEM/DAQ meeting for PHENIX upgrade (10/24/02) Outline Overview of PHENIX Si pixel detector ALICE1 chip readout.

— Test board for CBM01B2 baby detectors — Anton Lymanets & Johann Heuser CBM collaboration meeting GSI, 27 February 2008 Microstrip detector testing at.

EST-DEM R. De Oliveira 20 Dec., ‘04 Production of Gaseous Detector Elements  History of Gas Detectors in Workshop  Fabrication of GEM Detectors  Fabrication.

EP/ED group meeting1 ALICE PIXELS DETECTOR.

CERN Rui de OliveiraTS-DEM TS-DEM Development of Electronic Modules Rui de Oliveira CERN State of the art technologies for front-end hybrids.

Large area detectors Aida WP 9.2 RD51 WG6

Atsuhiko Ochi Kobe University

Assembly Procedure ALICE Outer Barrel Stave 14 Module 2 Cold Plates 1 StaveMarco Kraan Paul Kuijer.

Low Mass Rui de Oliveira (CERN) July

ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA.

Resistive protections Rui de Oliveira 09/12/15

Solid State Detectors for Upgraded PHENIX Detector at RHIC.

Konstantin Stefanov, Rutherford Appleton Laboratoryp. 1 1 mm Level 1 metal Polyimide Φ2Φ2 Φ2Φ2 Φ1Φ1 Φ1Φ1 To wire bonds Baseline Design Single level metal.

Proposal for the assembly of the PHOBOS ring counters (H.P. 3/20/98) I would like to propose and discuss with you an alternative layout and assembly procedure.

Vessel dimensions GTK assembly carrier Electrical connections Cooling pipes integration Vessel alignment with the beam Next steps Conclusion 3/10/20102.

Possible types of module Si/W CALORIMETER CONCEPT Si/W CALORIMETER CONCEPT G.Bashindzhagyan Moscow State University June 2002 Internal structure (not in.

The Development of the Fabrication Process of Low Mass circuits Rui de Oliveira TS-DEM.

10/7/2003Thomas Schneider1 Status report of CERN/PNPI Tooling support for PNPI M2R2 Prototype Plans towards the PRR.

Pixel Atsushi Taketani RIKEN RIKEN Brookhaven Research Center 1.Overview of Pixel subsystem 2.Test beam 3.Each Components 4.Schedule 5.Summary.

A.Cheremukhin (JINR, Dubna) CMS Preshower PRR, July 5-6, 2001, CERN1 Micro-module assembly -  -module elements - alignment of the silicon sensors to the.

Vessel dimensions GTK assembly carrier Electrical connections Cooling pipes integration Vessel alignment with the beam Next steps Conclusion 3/23/20102electro-mechanical.

WP7&8 Progress Report ITS Plenary meeting, 10 June 2014 LG, PK, VM, JR.

Atsushi Taketani 2005/06/03 VTX meeting 1 PIXEL BUS status 1.Circuit design 2.Design rule and design 3.Schedule.

DOE CD-2/3a Review of the BTeV Project – December 14-16, BTeV Pixel Detector Pixel Module Assembly and Half-Plane Assembly Guilherme Cardoso James.

Low Mass Alice Pixel Bus Rui de Oliveira TE/MPE/EM 6/9/20161Rui de Oliveira Alice worshop.

PACKAGE FABRICATION TECHNOLOGY Submitted By: Prashant singh.

Status of Prototype Preparation (I) Wander Baldini On behalf of the Ferrara SuperB group SuperB Workshop, LNF Dic. 2-nd 2009.

The STS-module-assembly:

Si Sensors for Additional Tracker

Update on the activities in Milano

Status on INTT bus extender R&D

ob-fpc: Flexible printed circuits for the alice tracker

Silicon Pixel Detector for the PHENIX experiment at the BNL RHIC

Pixel Status Mar 12nd 2012 Maki KUROSAWA RBRC.

Digital Integrated Circuits A Design Perspective

Production and test of Si sensors for W-Si sandwich calorimeter

General Capability Parameters Feature Y2017 Y2018 Y2019 Standard

Possible types of Si-sensor: SILICON CALORIMETRY FOR A LINEAR COLLIDER G.Bashindzhagyan, Il Park August Silicon sensor.

Presentation transcript:

1 Pixel Bus Development Atsushi Taketani RIKEN/RBRC 1.Who is working 2.Over view of pixel bus 3. Manufacture process 4. Issues 5. Development / Production Schedule

2 Who is working RIKEN –Design, Founding, and Coordination for PHENIX Soliton R&D –Fine pitch PCB manufacture. –Manufacturing Al bus Hiroshima Kokusai Gakuin University Research Institute of Advanced Technology –Expert of Aluminum for condensed matter physics KEK and their contractor –Parallel effort for R&D

3 ALICE Pixel BUS (a milestone) ALICE Pixel BUS structure 5 to 7 m Al 12 m Polyimide 5 m glue 15 m Al 5 m glue 12 m Polyimide 5 m glue 12 m Polyimide 5 m glue 12 m Polyimide 50 m Al Total radiation length = % X 0 5 to 7 m Al 5 m glue 12 m Polyimide 5 m glue Singal1 Singal2 Singal3 Signal 1; (Vertical line) line connected with pixel chip with wire bonding Signal 2; (Horizontal line) connected with vertical line with through hole Signal 3; (for SMD)

4 PHENIX Option Option 1 Option 2 Option 3 Easy (relatively) Aggressive Line spacing; 140 um pitch Material Budget; Cu;Total ~ % Al;Total ~ % Line spacing; 140 um pitch Material Budget; Cu;Total ~ % Al;Total ~ % Line spacing; 70 um pitch Material Budget; Cu;Total ~ % Al;Total ~ % Horizontal 2layer Vertical 2layer Horizontal 2layer Vertical 1ayer Alignment, Through hole Horizontal 1 layer Vertical 1layer Fine pitch

5 Manufacture Process Aluminum Polyimide 1 Glued Polyimide 2 Etching Polyimide 3 Glued Aluminum 4 Through hole 5 Alignment and Etching 6 Gold plating

6 List of Issues Pattern Etching Aluminum fine pitch pattern Through hole Small (~100micron) Filling conductive material Al - Ni - Au plating Making wire bonding pad Alignment of multiple layer Precise alignment

7 Etching Successfully for ALICE PIXEL bus pattern!!! 40 micron width, 120 micron pitch

8 Etching (2) Peal strength is OK by test. 10micron Polyimide + 5micron/15micron Glue (polyimide) + 12 micron Al Almost ready for production for ALICE BUS Possible for 40micron space pattern Possible to produce 5cm*60cm pattern

9 Through Hole (BVH method) Aluminum Polyimide Laser Chemical plating or Vacuum evaporation Tiring now and will have a result on next week

10 Al –Ni-Au plating 1.Al –Ni for hardening ground for wire bonding. Succeeded, I got a sample, sorry for no picture. 2.Ni-Au Trying now and will have a result on next week.

11 Alignment for multilayer bus By using alignment marks by machine By using through halls by human Developing adjustment machine by mid Sep. Polyimide Aluminum Resist Optics Mask Pattern On the movable table

12 Schedule Etching Done Through hall Done by 2 nd week of June Au plating Done by 2 nd week of June Alignment Machine will be ready at mid Sep. Test production on Mid Oct for ALICE Bus Preproduction for PHENIX on Mid Nov.

13 Alternative KEK and their contractor They will produce ALICE BUS on July. But no Al-Ni-Au plating. We are considering Cu version bus for PHENIX electrical test with readout chip and pilot module.