CSCI206 - Computer Organization & Programming Pipeline Datapath and Control zyBook: 11.6

The MIPS Pipeline

Implementation MIPS was designed to be pipelined All instructions are the same length (bits) allows fetch of next instruction immediately Operands aligned in memory constant length memory access Few (3) instruction formats simplifies decode Few addressing modes simplifies address generation

Splitting the datapath

Add Pipeline Registers Pipeline registers are clocked, just like the PC register. How many bits? Add Pipeline Registers

Executing a lw - cycle 1

Executing a lw - cycle 2

Executing a lw - cycle 3

Executing a lw - cycle 4

Executing a lw - cycle 5

Pipeline Registers with Control Control signals are computed in ID (decode) and then passed down the pipeline.

Pipeline Hazards Data Hazard Definition: when one instruction depends on the result of another: sub needs the result of the add ($s0)! add $s0, $t0, $t1 sub $t2, $s0, $t3

Pipeline diagram Sub tries to read $s0 and $t3 in cycle 3. clock cycle 1 2 3 4 5 6 7 8 add $s0, $t0, $t1 F D E M W sub $t2, $s0, $t3 Instructions Register write happens before read, so we can write and read in cycle 5! Sub tries to read $s0 and $t3 in cycle 3. The add doesn’t write the result until cycle 5! In the diagram above, the decode stage fails in cycle 3 and 4 (shown with a --) until $s0 is written in cycle 5 This is called a pipeline stall and should be avoided!

draw the pipeline diagrams Data Hazards→Reorder The best solution is to reorder instructions add $s0, $t0, $t1 sub $t2, $s0, $t3 addi $t4, $t4, 32 sll $t5, $t5, 5 add $s0, $t0, $t1 addi $t4, $t4, 32 sub $t2, $s0, $t3 sll $t5, $t5, 5 add $s0, $t0, $t1 addi $t4, $t4, 32 sll $t5, $t5, 5 sub $t2, $s0, $t3 Bad! Good! Better! draw the pipeline diagrams

Data Hazards→Forwarding Ex to Ex forward Consider the pipeline diagram, the sub needs $s0 at the beginning of cycle 4. Add computes this result in cycle 3. So we can forward (or bypass) the rest of the pipeline to deliver the value for $s0 just in time!

Data Hazards→Forwarding Mem to Ex forward The lw instruction is not complete until the end of the MEM stage. If the result is used immediately, we must insert a one cycle stall (or bubble). Then, we can forward the result directly from mem to ex.

Control Hazards Control Hazard When the result of one instruction changes the next instruction (i.e. branches) beq is computed using the ALU in the Ex stage What instruction do we fetch after the beq? add $4, $5, $5 beq $1, $2, 40 ???

Control Hazard Solution: beq calculation is easy (sub), so add a dedicated adder to the decode stage to immediately compute the zero result (in ID) Results in a one-cycle stall

Control Hazard Delay slot In MIPS, this obligatory stall after a branch is utilized for an instruction. The CPU will always execute the next assembly instruction and then execute the branch. (this is why we put a nop after branches & jumps in lab!)

Structural Hazard Structural Hazard If hardware cannot execute certain instructions at the same time MIPS avoids this for all integer instructions some floating point operations have structural hazards Reorder instructions to avoid else the CPU will stall to avoid

Pipeline Metrics Instructions per clock (IPC) or Ideally on a single core CPU we want IPC == 1, but hazards make this impossible in practice Instructions per clock (IPC) or clocks per instruction (CPI) recall