Chapter 8 Central Processing Unit 충남대학교 컴퓨터전공 http://sslab.cnu.ac.kr 이 철 훈

Fig. 8-1 Major component of CPU Chapter 7 Instruction CPU components Register Set : stores immediate data used during the execution of the instructions Arithmetic Logic Unit (ALU) : performs the required µoperations for executing the instructions Control Unit : supervises the transfer of information among the registers and instructs the ALU as to which operation to perform Fig. 8-1 Major component of CPU Computer System Architecture 1

General Registers Organization Chapter 8 General Registers Organization Register set with common ALU Computer System Architecture 1 Fig. 8-2 Register set with common ALU

General Registers Organization Chapter 8 General Registers Organization Control Word Tab. 8-1 Example of µoperations for the CPU Tab. 8-2 Encoding of ALU operations Computer System Architecture 1

General Registers Organization Chapter 8 General Registers Organization Example of µOperations R1 ← R2 - R3 Field : SELA SELB SELC OPR Symbol : R2 R3 R1 SUB Control word : 010 011 001 00101 Tab. 8-3 Example of µoperations for the CPU Computer System Architecture 1

Fig. 8-3 Block diagram of a 64-word stack Chapter 8 Stack Operation Stack : last-in first-out (LIFO) list Stack Pointer (SP) Push, Pop operations Register stack, Memory stack Register Stack Fig. 8-3 Block diagram of a 64-word stack Computer System Architecture 1

Fig. 8-4 Computer memory with program, data, and stack segments Chapter 8 Stack Operation Memory Stack Stack Limits Lower limit (4001), upper limit (3000) Fig. 8-4 Computer memory with program, data, and stack segments Computer System Architecture 1

Stack Operation Reverse Polish Notation (RPN) Example of RPN Chapter 8 Stack Operation Reverse Polish Notation (RPN) A + B Infix notation +AB Prefix or Polish notation AB+ Postfix reverse Polish notation Example of RPN A * B + C * D Infix notation AB*CD+ RPN Scan the expression from left to right When an operator is reached, perform the operation with two operands found on the left side of the operator Remove the two operands and operator, and replace them by the number obtained from the result of the operation Continue to scan the expression and repeat the procedure for every operator until there is no more operators → (A * B)CD*+ → (A * B)(C * D)+ → ((A * B) + (C * D)) Computer System Architecture 1

Fig. 8-5 Stack operations to evaluate 3 * 4 + 5 * 6 Chapter 8 Stack Operation Evaluation of Arithmetic Expressions Reverse Polish Notation, Combined with a stack arrangement of registers, is the most efficient way known for evaluating arithmetic expressions → employed in some calculators and in some computers Stack operations (3 * 4) + (5 * 6) Infix notation 3 4 * 5 6 * + parentheses-free RPN Fig. 8-5 Stack operations to evaluate 3 * 4 + 5 * 6 Computer System Architecture 1

Instruction Formats Common fields in instruction formats Chapter 8 Instruction Formats Common fields in instruction formats 1. Operation Code field that specifies the operation to be performed 2. Address field that designates a memory address or a processor registers 3. Mode field that specifies the way the operand or effective address is determined Three types of CPU organizations 1. Single accumulator organization ADD X // AC ← AC + M[X] // 2. General register organization ADD R1, R2, R3 // R1 ← R2 + R 3 // ADD R1, R2 // R1 ← R1 + R 2 // MOV R1, R2 // R1 ← R2 (or R2 ← R1) // 3, Stack organization PUSH X // Push the word at address X to the top of stack // ADD // Pop two top numbers, add them, push the result // Computer System Architecture 1

Instruction Formats Three-address instruction of X = (A + B) * (C + D) Chapter 8 Instruction Formats Three-address instruction of X = (A + B) * (C + D) ADD R1, A, B // R1 → M[A] + M[B] // ADD R2, C, D // R2 → M[C] + M[D] // MUL X, R1, R1 // M[X] ← R1 * R2 // Two-address instruction MOV R1, A // R1 → M[A] // ADD R1, B // R1 → R1, M[B] // MOV R2, C // R2 → M[C] // ADD R2, D // R2 → R2 + M[D] // MUL R1, R2 // R1 → R1 * R2 // MOV X, R1 // M[X] → R1 // Computer System Architecture 1

Instruction Formats One-address instruction Zero-address instruction Chapter 8 Instruction Formats One-address instruction LOAD A // AC ← M[A] // ADD B // AC ← AC – M[B] // STORE T // M[T] ← AC // LOAD C // AC ← M[C] // ADD D // AC ← AC + M[D] // MUL T // AC ← AC * M[T] // STORE X // M[X] ← AC Zero-address instruction PUSH A // TOS ← A // PUSH B // TOS ← B // ADD // TOS ← (A + B) // PUSH C // TOS ← C // PUSH D // TOS ← D // ADD // TOS ← (C + D) // MUL // TOS ← (A + B) * (C + D) // POP X // M[X] ← TOS // Computer System Architecture 1

Instruction Formats RISC instruction Chapter 8 Instruction Formats RISC instruction Only LOAD and STORE instruction between register and memory All other instructions are executed within the registers of the CPU LOAD R1, A // R1 ← M[A] // LOAD R2, B // R2 ← M[B] // LOAD R3, C // R3 ← M[C] // LOAD R4, B // R4 ← M[D] // ADD R1, R1, R3 // R1 ← R1 + R2 // ADD R3, R3, R4 // R3 ← R3 + R4 // MUL R1, R1, R3 // R1 ← R1 * R3 // STORE X, R1 // M[X] ← R1 / Computer System Architecture 1

Addressing Modes Purpose of Addressing Modes Instruction format Chapter 8 Addressing Modes Purpose of Addressing Modes 1. To give programming versatility to the user by providing such facility as pointer to memory, counters for loop control, indexing of data, and program relocation 2. To reduce the number of bitsin the addressing field of the instruction Instruction format Opcode + Mode + Address Addressing Modes 1. Implied mode : operands are specified implicitly in the instruction ‘complement accumulator’ 2. Immediate mode : operand is specified in the instruction itself MOV R1, #100 3. Register mode : operands are in the registers within the CPU MOV R1, R2 4. Register Indirect mode : instruction specifies a register whose contents give the address of the operand in memory - The address field of the instruction uses fewer bits to select a register than would have been required to specify a memory address Computer System Architecture 1

Chapter 8 Addressing Modes 5. Autoincrement or Autodecrement mode : similar to register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory MOV (R1 ++), (R2 ++) - effective in accessing data tables Effective Address : memory address obtained from the computation by the given addressing mode 1. Direct Address mode : effective address is equal to the address part of the instruction 2. Indirect Address mode : the address field of the instruction gives the address where the effective address is stored in memory 3. Relative Address mode : Program counter is added to the address part of the instruction to make effective address - branch-type instruction - results in a shorter field in the instruction format 4. Indexed Addressing mode : index register is added to the address part of the instruction to make effective address - base register holds a base address and the address field gives a displacement relative to this base address Computer System Architecture 1

Addressing Modes Numerical Example Chapter 8 Fig. 8-7 Numerical example for addressing mode Tab. 8-4 Tabular List of Numerical Example Computer System Architecture 1

Data Transfer and Manipulation Chapter 8 Data Transfer and Manipulation Three categories of computer instructions 1. Data transfer instruction 2. Data Manipulation instruction 3. Program control instruction Data transfer instructions (Tab. 8-5, 8-6) LD ADR // AC ← M [ ADR ] (direct address // ST @ADR // M [ ADR ] ← AC (indirect address // Data manipulation instructions (Tab. 8-7, 8-8, 8-9) 1. Arithmetic instructions INC, DEC, ADD, MUL, NEG, etc. 2. Logical and bit manipulation instructions CLR, COM, AND, OR, XOR, etc. 3. Shift instructions SHR, SHL, ROR, ROL, etc. Computer System Architecture 1

Fig. 8-8 Status register bits Chapter 8 Program Control Status Bit Conditions : condition code or flag bits C (carry) : 1 if the end carry C8 is 1 S (sign) : 1 if the MSB F7 is 1 Z (zero) : 1 if the output of ALU contains all 0’s V (overflow) : 1 if the exclusive-OR of last two carry is 1 Computer System Architecture 1 Fig. 8-8 Status register bits

Program Control Conditional Branch Instructions (Tab. 8-11) Chapter 8 Program Control Conditional Branch Instructions (Tab. 8-11) BZ Branch in zero // Z = 1 // BNZ Branch if not zero // Z = 0 // BC Branch if carry // C = 1 // BNV Branch if not overflow // V = 0 // numerical example ( A (11110000) – B (00010100)) Subroutine Call and Return Subroutine Call Subroutine Return Computer System Architecture 1

Program Control Program Interrupt Types of Interrupts Chapter 8 Program Control Program Interrupt Types of Interrupts ∗ external interrupts · I / O device, timer, … ∗ internal interrupts · illegal instruction or data (divide-by-zero, … ) ∗ software interrupts · special call instruction that behaviors like an interrupt rather than a subroutine call (INT 21H) The state of the CPU which must be saved ∗ the content of the program counter ∗ the content of all processor registers ∗ the content of certain status conditions The CPU does not respond to an interrupt until the end of an instruction execution Computer System Architecture 1

Reduced Instruction Set Computer (RISC) Chapter 8 Reduced Instruction Set Computer (RISC) CISC characteristics 1. A large number of instruction : 100 to 250 2. Some instructions that perform specialized tasks and are used infrequently 3. A large variety of addressing modes : 5 to 20 4. Variable-length instruction formats 5. Instructions that manipulate operands in memory 1. Relatively few instructions 2. Relatively few addressing modes 3. Memory access limited to load and store instructions 4. All operations done within the registers of the CPU 5. Fixed-length, easily decoded instruction formats 6. Single-cycle instruction execution 7. Hardwired rather than µprogrammed control Computer System Architecture 1

Reduced Instruction Set Computer (RISC) Chapter 8 Reduced Instruction Set Computer (RISC) Overlapped Register Window To avoid the need for saving and restoring register values and to provide the passing of parameters when procedure call and return Windows for adjacent procedures have overlapping registers that are shared to provide the passing of parameters and results Local registers are used for local variables. Common registers are used for exchange of parameters and results between adjacent procedures Only one register window is activated at any given time with a pointer indicating the active window G = the number of global registers L = the number of local registers in each window C = the number of registers common to two windows W = the number of windows ⇒ window size = L + 2C + G ⇒ register file = (L + C)W + G Computer System Architecture 1

Reduced Instruction Set Computer (RISC) Chapter 8 Reduced Instruction Set Computer (RISC) Computer System Architecture 1 Fig. 8-9 Overlapped register windows