Introduction toVLSI Programming Lecture 4: Data handshake circuits (course 2IN30) Prof. dr. ir.Kees van Berkel Dr. Johan Lukkien

Time table 2005 date class | lab subject Aug. 30 2 | 0 hours intro; VLSI Sep. 6 3 | 0 hours handshake circuits Sep. 13 handshake circuits assignment Sep. 20 Tangram Sep. 27 no lecture Oct. 4 Oct. 11 1 | 2 hours demo, fifos, registers | deadline assignment Oct. 18 design cases; Oct. 25 DLX introduction Nov. 1 low-cost DLX Nov. 8 high-speed DLX Nov. 29 deadline final report 11/30/2018 Kees van Berkel

Lecture 4 Outline: Recapitulation Lecture 3 Data encoding; push and pull handshakes Tangram assignment command Handshake components: handshake latch, transferrer, multiplexer, adder Handshake circuits & Tangram programs: fifo buffers and shift registers 11/30/2018 Kees van Berkel

Header: handshake circuit L=0 L=1 11/30/2018 Kees van Berkel

Sequencer realization x ar bk br cr ck ak Sequencer: area, delay, energy: Area: 5 gate equivalents Delay per cycle: 8 gate delays Energy per cycle: 10 transitions 11/30/2018 Kees van Berkel

Handshake signaling and data request ar active side passive side acknowledge ak data ad push channel versus pull channel request ar active side passive side acknowledge ak data ad 11/30/2018 Kees van Berkel

Handshake signaling: push channel time req ar ack ak early ad broad ad late ad 11/30/2018 Kees van Berkel

Data bundling In order to maintain event ordering at both sides of a channel, the circuit must satisfy data bundling constraint: for push channel: delay along request wire must exceed delay of data wire; for pull channel: delay along acknowledge wire must exceed delay of data wire. 11/30/2018 Kees van Berkel

Handshake signaling: pull channel When data wires are invalid: multiple and incomplete transitions allowed. req ar time ack ak early ad broad ad late ad 11/30/2018 Kees van Berkel

Tangram assignment x:= f(y,z) yw zw y f z   xw0 | x xr xw1 y f z   y f z   | x | x Handshake circuit 11/30/2018 Kees van Berkel

Four-phase data transfer time r / br ba / cr   b c ca / a bd / cd 1 2 3 4 5 11/30/2018 Kees van Berkel

Handshake latch [ [ w ; [w : rd:= wd] [] r ; r ] ] 1-bit handshake latch: wd  wr  rd  wd  wr  rd  wk = wr rk = rr x r w wd wr rd 11/30/2018 Kees van Berkel

N-bit handshake latch ... wr wd1 rd1 wd2 wk rd2 wdN rdN rr rk area, delay, energy area: 2(N+1) gate eqs. delay per cycle: 4 gate delays energy per write cycle: 4 + 0.5*2N transitions, in average 11/30/2018 Kees van Berkel

Transferrer ar ak a br ck bk cr  bd cd [ [ a : (b ; c)] ; [ a : (b ; cd:= bd ; c ; cd:= )] ] ar ak br bk bd ck cr cd  a b c 11/30/2018 Kees van Berkel

Multiplexer | Restriction: ar  br must hold at all times! a c b [ [ a : c ; a : (cd:= ad; c ; cd:= ) [] b : c ; b : (cd:= bd; c ; cd:= ) ] ] Restriction: ar  br must hold at all times! | a b c 11/30/2018 Kees van Berkel

Multiplexer realization control circuit data circuit 11/30/2018 Kees van Berkel

Logic/arithmetic operator [ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ] Cheaper realization (delay sensitive): [ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ; “delay” ; ad:=  ] f b c a 11/30/2018 Kees van Berkel

A one-place fifo buffer byte = type [0..255] & BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end BUF1 a b 11/30/2018 Kees van Berkel

A one-place fifo buffer byte = type [0..255] & BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end   ;  x b a   ; ;   a a  x x x x  b b 11/30/2018 Kees van Berkel

2-place buffer BUF1 a b c byte = type [0..255] & BUF1 = proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end & BUF2: main proc (a?chan byte & c!chan byte). begin b: chan byte | BUF1(a,b) || BUF1(b,c) end 11/30/2018 Kees van Berkel

Two-place ripple buffer 11/30/2018 Kees van Berkel

Two-place wagging buffer  byte = type [0..255] & wag2: main proc (a?chan byte & b!chan byte). begin x,y: var byte | a?x ; forever do (a?y || b!x) ; (a?x || b!y) od end 11/30/2018 Kees van Berkel

Two-place ripple register … begin x0, x1: var byte | forever do b!x1 ; x1:=x0; a?x0 od end 11/30/2018 Kees van Berkel

4-place ripple register byte = type [0..255] & rip4: main proc (a?chan byte & b!chan byte). begin x0, x1, x2, x3: var byte | forever do b!x3 ; x3:=x2 ; x2:=x1 ; x1:=x0 ; a?x0 od end 11/30/2018 Kees van Berkel

4-place ripple register x0 x1 x2 x3 x0 x0 x0 x1 x1 x2 x2 x3 x3 x3 area : N (Avar + Aseq ) cycle time : Tc = (N+1) T:= cycle energy: Ec = N E:= 11/30/2018 Kees van Berkel

Introducing vacancies … begin x0, x1, x2, x3, v: var byte | forever do (b!x3 ; x3:=x2 ; x2:=v) || (v:=x1 ; x1:=x0 ; a?x0) od end what is wrong? 11/30/2018 Kees van Berkel

Introducing vacancies forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0 ; a?x0)) ; x2:=v od or: forever do ((b!x3 ; x3:=x2) || (v:=x1 ; x1:=x0)) ; (x2:=v || a?x0) od 11/30/2018 Kees van Berkel

“synchronous” 4-p ripple register m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b m0 s0 m1 s1 m2 s2 m3 x0 b forever do (s0:=m0 || s1:=m1 || s2:=m2 || b!m3 ) ; ( a?m0 || m1:=s0 || m2:=s1 || m3:=s2) od 11/30/2018 Kees van Berkel

4-place wagging register x0 x1 x2 x3 y0 y1 a b a x0 x0 x1 x1 x2 b a b a a y0 y1 b b y0 y1 forever do b!x1 ; x1:=x0 ; a?x0 ; b!y1 ; y1:=y0 ; a?y0 od 11/30/2018 Kees van Berkel

8-place register 4-way wagging forever do b!u1 ; u1:=u0 ; a?u0 ; b!v1 ; v1:=v0 ; a?v0 ; b!x1 ; x1:=x0 ; a?x0 ; b!y1 ; y1:=y0 ; a?y0 od 11/30/2018 Kees van Berkel

Four 88 shift registers compared 11/30/2018 Kees van Berkel

Next session: lecture 5 Outline: Tangram overview Compilation: Tangram  Handshake Circuits Tools Demonstration Lab work: assignment “fifos and registers” 11/30/2018 Kees van Berkel