1. Introduction to Silicon Programming in the Tangram/Haste language
Material adapted from lectures by:
Prof.dr.ir Kees van Berkel
[Dr. Johan Lukkien]
[Dr.ir. Ad Peeters]
at the Technical University of Eindhoven, the Netherlands

2. Handshake protocol Handshake between active and passive partner
Communication is by means of alternating request (from active to passive) and acknowledge (from passive to active) signals
Active: send request, then wait for acknowledge
Passive: wait for request, then send acknowledge
Handshake circuits are a special class of asynchronous circuits.
Where ‘asynchronous’ stresses a propoerty that the circuit does not have (it is not synchronous), ‘handshake technology’ emphasizes the property that the circuits do have: namely the strict reliance on handshake protocols as a timing discipline.
A handshake protocol is a game between an active partner (indicated with the red bullet) and a passive partner (indicated with the green bullet). A handshake is initiated by the active partner by sending a request to the passive partner. This partner then “does what it is supposed to do” and, when completed, sends an acknowledgement back to the active partner.
Active
Passive

3. Handshake component: sequencer
Master
Sequencer
Task 1
Task 2
This animation shows a so-called “sequencer” component in operation. The task of a sequencer component, when activated from the top, is to first perform a handshake on the left-hand side, then on the right-hand side, and then to signal completion of its operation by completing the handshake with the top (activating) module.
This animation shows how handshake communication can be used to implement control functions, in this case sequencing. Similar components exist for parallel or conditional activation.

4. Four-phase handshake protocol
Circuit level implementation has separate wires for request and acknowledge
Four-phase handshake protocol implements return-to-zero of these wires
Active Side
Req := 1 ;
Wait (Ack);
Req := 0 ;
Wait (-Ack);
Passive Side
Wait (Req);
Ack := 1;
Wait (-Req);
Ack := 0;
Req
Ack

5. Handshake signaling active side passive side request ar acknowledge ak
time
event sequence: ar ak ar ak

6. Some handshake components a b
Repeater : [a : [b ; b] ]
Mixer : [ [ a : c ; [a : c] [] b : c ; [b : c] ] ]
Sequencer : [[a : (b ; b ; c) ] ; [a: c]] | a c b a ; b c

7. Handshake circuit: duplicator
For each handshake on a0 the duplicator produces two handshakes on a1
[[a0 : (a1 ; a1 ; a1) ] ; [a0: a1]]
cf. Handshake behavior sequencer.

8. Duplicator chains Assume aM toggles at frequency f.
Hence a0 toggles at frequency f / 2M.
Let Edup be the duplication energy per cycle.
Power of duplicator chain equals P = f Edup (1/2 + 1/4 + 1/ ) < f Edup

9. Handshake components: realization
From handshake notation to gate network in 8 steps:
Specify component in handshake notation.
Expand to individual boolean variables (wires).
Introduce auxiliary state variables (if required).
Derive a set of production rules that implements this refined specification.
Make production rules more symmetric (cheaper).
(Verify isochronic forks.)
Verify initialization constraints.
Analyze time, area, and energy.

10. For those who are interested in the details
Synthesis of Asynchronous VLSI Circuits
Alain J. Martin
Caltech CS-TR-93-28
PostScript link via async.bib (html version)
Programming in VLSI: From communicating processes to delay-insensitive circuits
Pages 1–64 in C.A.R. Hoare, ed.,
Developments in Concurrency and Communication

11. Handshake components realizations
Connector: trivial
Repeater: alternative ‘symmetrizations’
Mixer: isochronic forks
Sequencer: introduction of auxiliary variable
Duplicator: up to you?
Selector: up to you!

12. [ [ar] ; [ br ; [bk] ; br ; [bk] ] ; ak ]
Repeater realization  a b
Behavior: [a : [b ; b] ]
Expansion:
[ [ar] ; [ br ; [bk] ; br ; [bk] ] ; ak ]
Production rules:
false  ak ar  bk  br
true  ak bk  br
However, not initializable!

13. Repeater realizations

14. Sequencer realization
Specification: [(a : (b ; b ; c) ) ; (a: c)]
Expansion: [ [ar] ; br ; [bk] ; br ; [bk] ; cr ; [ck] ; ak ; [ar] ; cr ; [ck] ; ak ] a ; b c

15. Sequencer realizationx ar bk br cr ck ak
Sequencer: area, delay, energy
Area: 5 gate equivalents
Delay per cycle: 12 gate delays (8 with optimized C-element)
Energy per cycle: 12 transitions (10 with optimized C-element)

16. Parallel realization a || b c
[ a : ((b ; b) || (c c)) ; a ]
Cf. Join component
Expansion: [ [ar] ; ( (br ; [bk] ; br ; [bk]) || (cr ; [ck] ; cr ; [ck]) ) ; ak; [ar] ; ak] a || b c

17. Tangram assignment x:= f(y,z)yw zw y f z  
xw0 | x xr
xw1 y f z   y f z   | x | x
Handshake circuit

18. Transferrer ar ak a br ck bk cr  bd cd
[ [ a : (b ; c)] ; [ a : (b ; cd:= bd ; c ; cd:= )] ]
ar ak br bk bd ck cr cd  a b c

19. Logic/arithmetic operatorf b c a
[ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ]
Cheaper realization (delay sensitive):
[ [ a : (b || c) ] ; [ a : ((b || c) ; ad:= f(bd , cd ))] ; “delay” ; ad:=  ]

20. A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end
BUF1 a b

21. A one-place fifo buffer
byte = type [0..255]
& BUF1 = main proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end   ;  x b a   ; ;   a a  x x x x  b b

22. 2-place buffer BUF1 a b c byte = type [0..255]
& BUF1 = proc (a?chan byte & b!chan byte). begin x: var byte | forever do a?x ; b!x od end
& BUF2: main proc (a?chan byte & c!chan byte). begin b: chan byte | BUF1(a,b) || BUF1(b,c) end

23. Two-place ripple buffer

24. Median filter
median: main proc (a? chan W & b! chan W). begin x,y,z: var W & xy, yz, zw: var bool | forever do ((z:=y; y:=x) || yz:=xy) ; a?x ; (xy:= x<=y || zx:= z<=x) ; if zx=xy then b!x or xy=yz then b!y or yz=zx then b!z fi od end
Median a b

25. Greatest Common Divisor
gcd: main proc (ab?chan <<byte,byte>> & c!chan byte). begin x,y: var byte | forever do ab?<<x,y>> ; do x<y then y:= y-x or x>y then x:= x-y od ; c!x od end
GCD ab c

26. Tangram Compilation H C || E  · H · T = || · C ·T Tangram program T
Handshake circuit
VLSI circuit C E
Handshake process H ||
 · H · T = || · C ·T

27. VLSI programming of asynchronous circuits
behavior,
area, time, energy,
test coverage
Tangram program
feedback
compiler
simulator
Handshake circuit
expander
Asynchronous circuit
(netlist of gates)

28. Tangram tool box Let Rlin4.tg be a Tangram program: htcomp -B Rlin4
compiles Rlin4.tg into Rlin4.hcl, a handshake circuit
htmap Rlin4
produces Rlin4*.v files, a CMOS standard-cell circuit
htsim Rlin4 a b
executes Rlin4.hcl with files a, b for input/output
htview Rlin4
provides interactive viewing of simulation results

29. Greatest Common Divisor
gcd: main proc (ab?chan <<byte,byte>> & c!chan byte). begin x,y: var byte | forever do ab?<<x,y>> ; do x<y then y:= y-x or x>y then x:= x-y od ; c!x od end
GCD ab c