Analog-to-Digital Converters

Slides:

Advertisements

Similar presentations

Counters Discussion D8.3.

Advertisements

CDA 3100 Recitation Week 11.

Shift Registers Module M11.1 Section 7.3.

Table 7.1 Verilog Operators.

Pulse-Width Modulated DAC

A/D Converter Control Discussion D8.6. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

Analog-to-Digital Converters

Analog-to-Digital Converters Lecture L11.2 Section 11.3.

A/D Converter Datapaths Discussion D8.4. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

Binary-to-BCD Converter

Sequential Circuit Introduction to Counter

Mantıksal Tasarım – BBM231 M. Önder Efe

Registers & Counters M. Önder Efe

Lecture 9. - Synchronous Devices require a timing signal. Clock generated Interval Timer Microprocessor Interval Timer Clk PCLK = MHz PCLK (for.

Designing Combinational Logic Circuits in Verilog - 2

Binary-to-BCD Converter

Registers CPE 49 RMUTI KOTAT.

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

Analog to Digital conversion. Introduction  The process of converting an analog signal into an equivalent digital signal is known as Analog to Digital.

Figure A flip-flop with an enable input. D Q Q Q R Clock E 0 1.

Princess Sumaya Univ. Computer Engineering Dept. Chapter 6:

Digital Design Lectures 11 & 12 Shift Registers and Counters.

Digital Logic Design.

Decoder A01-A31 address, LWORD*, IACK*, AM0-AM5 SN74LS245 Interrupter 5V-3.3V Level change Xilinx CPLD 125MHz XC95288 JTAG VMEbus interface 2*18-Bits 133MHz.

Digital Fundamentals Tenth Edition Floyd Chapter 9.

Water Flow GROUP A. Analogue input voltage results: Motor Input voltage( V) pin 12 Analogue input voltage (V) Display number

1 CS 151: Digital Design Chapter 3: Combinational Logic Design 3-1Design Procedure CS 151: Digital Design.

Digital Electronics.

Capture and record 1GHz signal (Block Diagram)

CSE 171 Lab 11 Digital Voltmeter.

Department of Electronic & Electrical Engineering Further work? Simple Voltmeter. ● Analogue to Digital converter (MCP3001 SPI ) ● Analogue → 10bit binary.

ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Fall 2000 Chapter 5 – Part 2 Tom Kaminski & Charles.

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 7 – Part 2.

ULTRA LOW CURRENT MEASUREMENT SYSTEM. A full diagram of a mass spectrometer.

Chapter 8 Solving Larger Sequential Problems.

0808/0809 ADC. Block Diagram ADC ADC0808/ADC Bit μP Compatible A/D Converters with 8-Channel Multiplexer The 8-bit A/D converter uses successive.

Lecture 8. ALU, Shifter, Counter,

Decoders A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence.

Introduction to FPGAs Getting Started with Xilinx.

Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.

Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.

Supplement on Verilog for Algorithm State Machine Chart

Figure 8.1. The general form of a sequential circuit.

EKT 124 / 3 DIGITAL ELEKTRONIC 1

Digital Fundamentals Abdul Hameed

FIGURE 6.1 Four‐bit register

Supplement on Verilog Sequential circuit examples: FSM

EKT 221 – Counters.

EKT 221 : Digital 2 COUNTERS.

Sequential Logic Counters and Registers

Principles & Applications

Registers and Counters

Logic Design Review – 2 Basic Combinational Circuits

Lecture 18 PicoBlaze I/O Interface

Shift Registers Lecture L8.6 Section 8.3.

CSE 171 Lab 11 Digital Voltmeter.

Digital Control Systems Waseem Gulsher

ESE 437: Sensors and Instrumentation

Registers and Counters

FIGURE 1: SERIAL ADDER BLOCK DIAGRAM

Overview Part 1 - Registers, Microoperations and Implementations

Supplement on Verilog Sequential circuit examples: FSM

Register-Transfer Level Components in Verilog

Switching Theory and Logic Design Chapter 5:

The Verilog Hardware Description Language

14 Digital Systems.

Test Fixture Template module testfixture ; // data type declaration

Registers and Counters

Registers and Counters

Registers and Counters

Presentation transcript:

Analog-to-Digital Converters Lecture L11.2 (Verilog) Section 11.3

Analog-to-Digital Converters Converts analog signals to digital signals 8-bit: 0 – 255 10-bit: 0 – 1023 12-bit: 0 – 4095 Successive Approximation

Method of Successive Approximation

Implementing Successive Approximation

ADC0831 8-Bit Serial I/O A/D Converter

ADC0831 Timing

Voltmeter Logic Block Diagram

module binbcd9(B,P); input [8:0] B; output [10:0] P; reg [10:0] P; reg [19:0] z; integer i; always @(B) begin for(i = 0; i <= 19; i = i+1) z[i] = 0; z[11:3] = B; for(i = 0; i <= 5; i = i+1) if(z[12:9] > 4) z[12:9] = z[12:9] + 3; if(z[16:13] > 4) z[16:13] = z[16:13] + 3; z[19:1] = z[18:0]; end P = z[19:9]; endmodule

Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Q6 & Q7 (CS) Data Out (DO) !Q3 shift (S) 7 6 5 4 3 2 1 0 !Q3 shift (S) [Q7..Q4] == 10 (Capture) !Q3 display (D)

Q1 Q0 1.0 MHz Q2 0.5 MHz Q3 0.25 MHz 2.0 MHz Clock 4.0 MHz

Q3 CLK Q7 Q6 CS DO Xilinx XC95108 PC84 CPLD Clock Divider Counter Q7..Q0 4 MHz Clock ADC0831 Interface

Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Q6 & Q7 (CS) Data Out (DO) !Q3 shift (S) !Q3 display (D) [Q7..Q4] == 10 (Capture) Q6 & Q7 (CS) Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Data Out (DO) 7 6 5 4 3 2 1 0 !Q3 shift (S)

Count Detect Logic (Q7..Q4 = 10102) Capture Xilinx XC95108 PC84 CPLD Clock Divider Counter Q7..Q0 4 MHz Clock Q3 Q7 Q6 CLK CS DO ADC0831 Interface Display Register D7..D0 Clock Load Shift Register S7..S0 Data !Q3

Simulation of adconv

Binary-to-BCD Converter 7-Segment Decoder 7 Voltage Display a..g Binary-to-BCD Converter Hundreds Tens Units 7-Segment Decoder 7 Voltage Display a..g Xilinx XC95108 PC84 CPLD Display Register D7..D0 Clock Load (Shift Register S7..S0) (Capture) (!Q3) dpt 1