EEL 3705 / 3705L Digital Logic Design Spring 2007 Instructor: Dr. Michael Frank Module #15: Finite-State Machine Design (Thanks to Dr. Perry for some slides)

Dr. Perry’s Slides Following are some old slides by Dr. Perry on Finite State Machines, left over from previous semesters…

Finite State Machine (FSM) General Models

Moore FSM General Block Diagram Next State Present State Output Vector Input Vector Clock Feedback Path Reset CL= Combinational Logic Cloud Reg= D Registers

Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Mealy FSM Block Diagram and State Equations Next State Present State Input Vector Output Vector Feedback Path Output Y is also a function of input X

Mealy-Moore FSM Block Diagram and State Equations Present State Next State Input Vector Mealy Outputs Moore Outputs

State Diagrams

State Bubble

State Bubble Example State name = S0 State value = 00 Conditional Transition Unconditional Transition State name = S0 State value = 00 Y = 0 for this state We leave this state if upn=1, We remain in this state if upn=0

FSM Examples

Example– 2-bit Up Counter State Diagram Clock is implied

Example – 2-bit Up Counter State Table State Value Assignment Let S0 = 00 S1 = 01 S2 = 10 S3 = 11 ps ns y S0 S1 S2 1 S3 2 3 Output Vector Let S0 = reset state

Example – 2-bit Up Counter Truth Table ps1 ps0 ns1 ns0 y1 y0 1

Example – 2-bit Up Counter Excitation Equations

Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example No H Logic needed

Logic Diagram

Flash Animation

Example 3– 2-bit Down Counter State Diagram Clock is implied

Example – 2-bit Down Counter State Table Let S0 = 00 S1 = 01 S2 = 10 S3 = 11 ps ns y S0 S3 S2 3 S1 2 1 Let S0 = reset state

Example – 2-bit Down Counter Truth Table ps1 ps0 ns1 ns0 y1 y0 1

Example – 2-bit Down Counter Excitation Equations

Recall Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example

Logic Diagram

Example 4 – 2-bit Up/Down Counter State Diagram

Example – 2-bit Up/Down Counter State Diagram Shorthand Notation

Example – 2-bit Up/Down Counter State Table ps ns upn y S0 S1 S3 S2 1 2 3 Let S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let S0 = reset state

Example – 2-bit Up/Down Counter Truth Table upn ps1 ps0 ns1 ns0 y1 y0 1

Example – 2-bit Up/Down Counter Excitation Equations

Recall Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Diagram Reg Block X Vector F Logic Y Vector H Logic

Logic Diagram

Example 5– 3-bit Arbitrary Counter Design a 3-bit arbitrary counter that will count in the following sequence 3,2,3,1,2,3 If a state is not used reset it to state zero. How may states do we have? How many registers do we need? How many bits do we need for Y?

Example 5– 3-bit Arbitrary Counter State Diagram

Example – Arbitrary 3-bit Counter State Table Assign State Values Let S0 = 000 S1 = 001 S2 = 010 S3 = 011 S4 = 100 S5 = 101 S6 = 110 S7 = 111 ps ns y S0 S1 3 S2 2 S3 S4 1 S5 S6 S7 Let S0 = reset state

Develop Truth Table

Example – 2-bit Arbitrary Counter Develop Excitation Equations -- F Logic

Develop Excitation Equations for Y

Example – 2-bit Arbitrary Counter Excitation Equations -- H Logic

Recall Moore FSM State Equations Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

Logic Circuit H REG F

Logic Circuit

Simulation

Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET) State Diagram Clock is implied

Example – 2-bit Up/Down Counter with Enable and SRESET Functional Table srn en upn Function d Synchronous Reset (sreset) 1 Hold Count Up Count Down Highest Level of Priority Lowest Level of Priority

State Table Srn En upn ns d S0 1 ps ps+1 ps -1

Truth Table (5 variables!!) Although, we could design this circuit directly from the truth table we will use design partitioning.

Moore FSM Architecture Next State Present State Output Vector Input Vector Feedback Path

to create the “new” design. Partitioned Design srn We have en Srn En ns d S0 1 PS Count Note, with the partitioned design we can “reuse” already designed submodules to create the “new” design.

Top Level Block Diagram

UP/Down Logic Logic Circuit Symbol

Register Block Symbol Logic Circuit

2 Bit 4x1 Mux Circuit Symbol

1-bit 4x1 Mux Logic Circuit Symbol

1-bit 2x1 Mux Logic Circuit Symbol

Top Level Block Diagram

Simulation

Example 6 – FSM Controller State Diagram

Truth Table for NS Truth Table

Kmaps for NS1 and NS0 NS1 NS0

Truth Table and Equations for Y Recall, Moore FSM, so Y will Not be a function of T By Inspection

Logic Circuit H REG F

Simulation