CSC Trigger Primitives Test Beam Studies Main Test Beam 2003 Goals: Verify the peripheral crate electronics (mainly DMB/TMB) are ready for production. Complete a trigger electronic chain test from CSCs all the way to the Track-Finder trigger. Subsidiary Goals: Find and fix hardware/firmware bugs and annoyances. Find and fix software bugs and annoyances. (Re-)demonstrate proper triggering and DAQ readout. Shake out new OO software package.

Beam Test Setup PC TRIDAS beam S1 S2 S3 CSC 1 CSC 2 TTC crate Trigger primitives DAQ Data PC Track finder Crate Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU TRIDAS beam S1 S2 S3 CSC 1 CSC 2

Beam Test Setup / 2 CSC’s, all on-chamber boards Peripheral crate From front end cards 2 TMBs and DMBs MPC CCB + TTCRx 2 CSC’s, all on-chamber boards Peripheral crate Track Finder CMS readout board Up to 80K events read out in 2.6s spill

Typical Muon Event (CSC1 tilted)

2003 Test Beam Chronology Phase I – structured beam May 23-June 1 ALCT timing tests CLCT and TMB studies High-rate tests Phase II – unstructured beam June 13-28 Low-rate and high-rate tests Phase III – additional structured beam September 18-22 Trigger optical link data transmission tests (MPC to SRSP)

Phase I Results Optimal timing found Fairly high efficiency (~98-99%) achieved Peripheral crate system basically working as desired Chamber angle, HV, threshold scans

2003 Synchronous Beam Structure 48 bunches 25 ns bunch spacing bunch width 3-5 ns SPS orbit period 1.2 ms 23 ms Structure repeats during 2.6 s spill length

Bunch Structure, ALCT Delay Tuning Expect muons in 48 out of 924 bx verified by CLCT bxn from data BX efficiency vs. ALCT delay setting 0-31 ns Chamber 1 Chamber 2

BX Distributions With Optimal Anode Delays Note logarithmic scale Cathodes: Data mostly in 3 bx (no fine time-adjustment possible) Anodes: Data 98.7% in 1 bx (after fine time-adjustment) Chamber 1 Chamber 2

CLCT Positions Relative position of key half strip from CLCTs from chamber 2 vs. Chamber 1 Note: Chamber 1 is vertically higher than Chamber 2 (thus the offset in position). Zoom

LCT Efficiency vs. Comp. Thresh. HV=3600v

LCT Efficiency vs. HV

Expected LCT rate at LHC < 25 KHz (ME1/1) Trigger Rate Tests data consistent with dead-time = 225 ns Chamber #1 CLCT 500 1,000 1,500 2,000 2,500 3,000 Beam Intensity (KHz) CLCT Rate (KHz) SLHC (10xLHC) SLHC (10xLHC) Expected LCT rate at LHC < 25 KHz (ME1/1)

Number of LCTs (Run 529) Anodes show ~10% 2-LCT events Cathodes show ~4% 0-LCT events Early run, before timing tuned

Look at 2-ALCT events Differences: Bunch crossing counter Wire group

An Event w/ 2 Chamber 1 ALCTs Anode hits satisfy 6-hit requirement in 2 adjacent key wire groups

Patterns and Quality in ALCT and TMB Logic xxx__ ly 0 _xx__ ly 1 __x__ ly 2 __xx_ ly 3 __xxx ly 4 __xxx ly 5 ALCT Pattern TMB Patterns x___ xx__ _x__ _xx_ __x_ pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 pattern 6 __x_ ly 0 __x_ ly 1 _xx_ ly 2 _x__ ly 3 xx__ ly 4 x___ ly 5 pattern 7 Qualities for ALCT and CLCT: Quality=3 6 layers in pattern Quality=2 5 layers in pattern Quality=1 4 layers in pattern Quality=0 <=3 layers in pattern

Half-/Di-Strip CLCT Patterns Nominally phi_b=0, but small tilts, esp. chamber 2

CLCT Quality, Pattern vs. Phi_b Quality (layers) Pattern Phi_b (tilt)

Test Beam Periods 2&3 Timing-in procedures improved & documented Very high efficiencies achieved Highest trigger efficiency of 99.9% required low rate (few kHz) 2-chamber “excellent event” (CFEB, CLCT, ALCT) efficiency limited to 99% due to CFEB timing Improved scans taken: Angle scan HV scan Comparator threshold scan Pattern requirements scan Logic scope read out on most data True time history of LCTs read by SR/SP input FIFO (see Darin/Alexei talks).

CLCT Pattern Requirements Example – “excellent event” (2xCFEB, 2xCLCT, 2xALCT) percentages: Di-strip Pretrig. Layers Half-strip Pretrig. Layers Pattern Layers Run # Excellent Event Eff. (off) 4 1 1133 98.9% 1134 98.8% 3 1132 98.0% 1131 97.9% 1126 94.7% 1119 1120 2 1121 92.6%

Digital Comparisons LCTs vs. Simulation Simulation “DIGIs” start from raw hit data ORCA classes used Added modifications to reflect test beam TMB firmware (due to FPGA limitations) In principle, tests ALCT, CLCT, and TMB logic. So far, mainly a good debugging tool for simulation Present level of ALCT disagreement: ALCT Wire Group: 1.75%/1.99% ALCT Quality: 0.15%/0.41% CLCT disagreement ~10% (see plots on right)

Comparison of LCTs to Simulation ORCA simulation has some shortcomings and needs updating: Pretrigger # of layers is still hardcoded. Was varied during test beam data-taking No drift delay in ORCA after pretrigger – just uses any hits within 4 bx of some reference bx. ORCA logic selects highest quality only, doesn’t prefer half-strip patters to di-strip patterns as per hardware. Simplification for test beam TMB allows only 1 CLCT per CFEB These are being addressed right now.

Comments on Results Timing in the system takes effort but getting easier (~2 weeks -> 1 week -> 2 days) Almost everything can be done remotely with software. Procedures must really be streamlined to deal with 468 chambers… When timed in and experts are present: Electronics hardware is reliable (nothing flaky). Data quality is terrific, esp. compared to other CMS subsystems… Trigger and readout efficiencies are very good. It will be hard work to streamline for 468 chamber operation…