Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ EE5342 – Semiconductor Device Modeling and Characterization Lecture 28 April 28, 2010 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

Introduction Self heating of the transistor is proportional to the power dissipated. Temperature Rise = ΔT = Rth ∙Power The VBIC model was developed to simulate the BJT such that the device temperature tracked power dissipation in real time. Other circuit simulators which accommodate thermal resistance are HICUM MEXTRAM L28 04/28/10

Rth Estimation for a Small Diode-isolated BJT Device VBE=0.87 V and VCE=20 V, RTH = 341 C/W L28 04/28/10

VBIC Model Highlights Self-heating effects included dt tl Self-heating effects included Improved Early effect modeling Quasi-saturation modeling Parasitic substrate transistor modeling Parasitic fixed (oxide) capacitance modeling An avalanche multiplication model included Base current is decoupled from collector current L28 04/28/10

2-D Isotherm Plot- Lines Connecting Points of Equal Temperature 2-D Isotherm plots for a structure scaled to be the same as the P10 1X2X1 device. L28 04/28/10

Thermal Model of a SiGe HBT The structure of a typical SiGe HBT (Heterojunction Bipolar Transistor) [1] The Electrical circuit topology (Cauer network) for the thermal analogy model Oxide L28 04/28/10

One Dimensional Heat Flow in Silicon AMBIENT HEAT SILICON A silicon structure can be sub-divided into several silicon slabs. Each section contributes to the total Rth and Cth of the structure. If each section is of equal volume, their individual Rth and Cth should be equal in value. To correspond to uniform heat flow, each section can be represented by a thermal resistance and half the total capacitance on each node of the resistor. Cth 2 Rth L28 04/28/10

The Distributed Nature of the Heat Flow The corresponding CTh /2 capacitors are aggregated at each node. Note that the “ambient end” CTh /2 is short-circuited. The distributed equivalent circuit analogy simulation is obtained from the following network. Rth n Cth 2n Add formula Rth = Total Thermal resistance for the silicon structure Cth= Total Thermal capacitance of the silicon structure n = number of sections A=area cp= thermal capacitance ρ=density t= thickness kp= thermal conductance L28 04/28/10

Comparison of Circuit Analogy to Davinci Simulation of the Heat Flow Considering a silicon structure of size 3.7umx2.5um x10um Dividing the structure into 10 sections. where i=1,2,3…n, n= number of sections Dotted line=Davinci simulation measurement Solid line = equivalent circuit simulation L28 04/28/10

Approximating the Distributed Circuit With a Single Pole Model Converting the 10 element distributed model to a 1 pole model: RTotal=Rth at ‘dc’ ΔQTotal =(cp)(ρ)Tavg For total heat consumption. Heat stored corresponds to charge stored for the equivalent circuit. How the davinci simulation and parameter , rth total , cth total add slide for simulation using calculation. Parameter values of the circuit simulation. Rth n Cth 2n L28 04/28/10

Comparison of Circuit Analogy to Davinci Simulation for Heat Flow

(cont’d) Top of the tub Top of the oxide Top of the wafer Results from equivalent circuit simulations Results from Davinci Simulation Results from device measurement Foster network Results from device measurement Cauer network Top of the tub Top of the oxide Top of the wafer L28 04/28/10

Circuit used for simulations

dt for VBIC-R1.5 model Model: VBIC-R1.5. “selft” flag set to 1. No optimization done. No external circuit connected. Rth=5.8E+0 Cth=96E-12 L28 04/28/10

VBIC-R1.5 Y11 plot (standard data)

VBIC-R1.5 Y11 plot (standard data)

VBIC-R1.2 Y11 plot (optimized data) For optimized data refer slide “Model Parameters”. Circuit used is shown in “Circuit for Y parameters (optimized data)” slide. fc Τ fc1= 2E3 7.962E-05 fc2= 9.25E4 1.721E-06 fc3= 3.2E6 4.976E-08 Fc4=2E3 Fc5=1E5 1.592E-06 Fc6=4E6 3.981E-08 fc7= 2E3 fc8= 1E5 fc9=4E6 L28 04/28/10

Spreadsheet for Calculating the Rth and Cth Calculations mentioned in the previous slides have been implemented in an Excel spreadsheet. The Cauer to Foster network transformation is done.  The spreadsheet takes the dimensions of different layers of the devices and gives corresponding Cauer and Foster network values. This enables the calculation of time constants which can be converted into a single pole. The characteristic times for the Foster network appear on a impulse response plot. Fig. 7. Electrical equivalent Cauer network of the HBT Fig. 8. Electrical equivalent Foster network of the HBT L28 04/28/10

Effect of Rth on current feedback op-amp settling time + vIN = 1 V P-P, t = 200 m-sec 500 W vOUT 100 W L28 04/28/10

Current Feedback Op Amp Data (LMH6704) Switching Offset

LMH6550 impulse thermal characteristics LeCroy sampling oscilloscope (1MW input mode) Maximum averaging (10000) Input nominally +/- 1V with 50 micro-sec period and 50% duty cycle. Fractional Gain Error = FGE L28 04/28/10

vIN Rising Response vIN FGE vOUT L28 04/28/10

vIN Falling Response vOUT FGE vIN L28 04/28/10

Current Feedback Op-Amp (CFOA) with Simple Current Mirror (CM) Bias sup L28 04/28/10

Large-signal Output Voltage Transient Analysis for CFOA with Simple CM Biasing

Hypothesis: The Thermal Tail is a Linear Superposition of the Contribution from each Individual Circuit Stick The contribution of individual transistor to the total thermal tail. Used six stick classifications according to transistor type and functionality. i.e. Q10stk3-pnp-bf and Q11stk4-npn-cm Enabled the self-heating effect in the stick of interest and disabled the self-heating effect of the remaining transistors. Simulated the contribution of each individual stick. The total thermal tail simulated is essentially the sum of the individual thermal tail contributions of each circuit stick. L28 04/28/10

The Hypothesis Supported Area x1 Area x8 Thermal Tail (uV/V) High-to-Low Low-to-High stk2-npn-bf (Q5) -822 842 -124 128 stk2-pnp-bf (Q6) -727 712 -101 98 stk2-npn-cm (Q2) -89 91 -11 12 stk2-pnp-cm (Q4) -91 89 -10 9 stk3-npn-bf (Q7) -877 850 -111 106 stk3-pnp-bf (Q8) -783 808 115 stk4-npn-cm (Q12) -1213 1217 -172 173 stk4-pnp-cm (Q10) -1075 1073 -159 158 stk5-npn-bf(Q13) 13 -13 2 -2 stk5-pnp-bf(Q14) -4 4 -1 1 stk5-npn-cm(Q18) 16 -15 stk5-pnp-cm(Q17) -5 stk6-npn-bf(Q15) stk6-pnp-bf(Q16) added total -5658 5661 -796 796 simulated total -5311 5313 -789 789 L28 04/28/10

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Heterojunction Electrostatics Eo qfp qfn EC,p DEC EC,n EF,p EF,n EV,p EV,n DEV -xn xp L28 04/28/10

Poisson’s Equation Ex x -xn xp L28 04/28/10

Heterojunction electronics

Heterojunction electronics (cont)

Heterojunction electronics (cont)

Heterojunction depletion widths

References Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”, from http://eesof.tm.agilent.com/pdf/VBIC_Model_Extraction.pdf http://www.fht-esslingen.de/institute/iafgp/neu/VBIC/ Avanti Star-spice User Manual, 04, 2001. Affirma Spectre Circuit Simulator Device Model Equations Zweidinger, D.T.; Fox, R.M., et al, “Equivalent circuit modeling of static substrate thermal coupling using VCVS representation”, Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s): 1198 -1206 L28 04/28/10

Thermal Analogy References [1] I.Z. Mitrovic , O. Buiu, S. Hall, D.M. Bagnall and P. Ashburn “Review of SiGe HBTs on SOI”, Solid State Electronics, Sept. 2005, Vol. 49, pp. 1556-1567. [2] Masana, F. N., “A New Approach to the Dynamic Thermal Modeling of Semiconductor Packages”, Microelectron. Reliab., 41, 2001, pp. 901–912. [3] Richard C. Joy and E. S. Schlig, “Thermal Properties of Very Fast Transistors”, IEEE Trans. ED, ED-1 7. No. 8, August 1970, pp. 586-599. [4] Kevin Bastin, “Analysis and Modeling of self heating in SiGe HBTs” , Aug. 2009, Masters Thesis, UTA. [5] Rinaldi, N., “On the Modeling of the Transient Thermal Behavior of Semiconductor Devices”, IEEE Trans-ED, Volume: 48 , Issue: 12 , Dec. 2001; Pages:2796 – 2802. L28 04/28/10

Simulation … References [1] E. Castro, S. Coco, A. Laudani, L. LO Nigro and G. Pollicino, “A New Tool For Bipolar Transistor Characterization Based on HICUM”, Communications to SIMAI Congress, ISSN 1827-9015, Vol. 2, 2007. [2] K. Bastin, “Analysis And Modeling of Self Heating in Silicon Germanium Heterojunction Bipolar Transistors”, Thesis report, The University of Texas at Arlington, August 2009. L28 04/28/10

AICR Team at University of Texas Arlington - Electrical Engineering Current Earlier Contributors Ronald L. Carter, Professor W. Alan Davis, Associate Professor Howard T. Russell, Senior Lecturer Ardasheir Rahman1 Ratan Pulugurta1 Xuesong Xie1 Arun Thomas-Karingada2 Sharath Patil2 Valay Shah2 Kevin Bastin, MS Abhijit Chaugule, MS Daewoo Kim, PhD Anurag Lakhlani, MS Zheng Li, PhD Kamal Sinha, PhD 1PhD Student 2MS Student L28 04/28/10