Compiler Back End Panel Robert Geva Intel Compiler Lab 2018/11/24

Back End Compiler Panel 1) Are compiler code generation techniques going to transition along with the hardware transition from multi-core to many-core and hybrid systems and at what speed? 2) What information do you need from a Compiler Intermediate Format to efficiently utilize multi-core, many-core and hybrid systems that is not available from traditional languages like C, C++, or F90? Are you looking at directive-based or library-based approaches or is there another approach that you like? 3) Is embedded global memory addressing (like Co-Array Fortran) to be widely available and supported even on distributed memory systems? 4) What kind of hybrid systems or processor extensions are going to be supported by your compiler's code generation suite? 5) What new run-time libraries will be available to utilize multi-core, many-core, and hybrid systems and will they work seamlessly through dynamic linking?

Are compiler code generation techniques going to transition along with the hardware transition from multi-core to many-core and hybrid systems and at what speed? JIT compiling Ct: Research technology for a data parallel language Forward scaling to future architectures Save costly memory copying by delayed code generation Validation Multiple targets 11/24/2018

Is “limit” loop invariant? Are you looking at directive-based or library-based approaches or is there another approach that you like Is “limit” loop invariant? Needs more work Here’s my code Interactive Compiler technology to Guide the programmer to write serial code with directives and restructuring, leading to automatic parallelism 11/24/2018

Is embedded global memory addressing (like Co-Array Fortran) to be widely available and supported even on distributed memory systems? Minimize changes to programming practices Use familiar concepts, existing programming languages, integrate into advanced platform technologies Goals Data parallel language: Start programming from data parallelism perspective, use array notations. Tool chain will transform and target a CPU and Larrabee combination Offload language: Start with task parallelism, and use directives to offload computation Solutions 11/24/2018

What kind of hybrid systems or processor extensions are going to be supported by your compiler's code generation suite? Existing SIMD SSE, SSE2, SSE3, SSE4 LRB new instructions 512 width Masked operations Broadcasts, swizzles Advanced Vector eXtensions 256 width 3 operand, non destructive Enhanced data re-arrangement 11/24/2018

What new run-time libraries will be available to utilize multi-core, many-core, and hybrid systems and will they work seamlessly through dynamic linking? Resource coordination and task scheduling http://channel9.msdn.com/pdc2008/TL22/ Generic algorithms, equivalent to language extensions Domain specific libraries Including math libraries New domains, natural language processing, gesture recognition DLL hell? No good news 11/24/2018