1. Compiler Front End Panel
Robert Geva
Speaking for myself, working as a
parallel programming architect Intel Compilers and Languages
2018/12/8

2. 1. Language Support for Parallelism
Data Parallelism
Integration of Firetown (Ct) and RapidMind
Array notation for C/C++
Semantically mandating data parallelism
Task Parallelism
Integration of Cilk++ and TBB
A Cilk++ program is serialize- able
Well defined points where execution becomes async
Minimal addition to baseline language
Defense against data races
Safe, friendly parallel programming is achievable
12/8/2018

3. 2. Performance Provided by System SW
Firetown will use JIT compilation
Adapt to HW, vector ISA
Profile guided optimization – take the data into account
TBB, Cilk rely on the programmer to write small units of work, units of scheduling (over decomposition)
User mode work stealing scheduler provides dynamic load balancing
Research project:
CPU performance counters made available to a JIT compiler, allow dynamic re-optimizations
Working to move performance responsibility from the programmer to system SW
12/8/2018

4. 4. Tools Discovery tools Intel Parallel Advisor:
read the source code
Guide though elimination of potential data races
Recommend opportunities to introduce parallelism based on program loop structure, targeting outer loops
Guided Auto Parallelism:
Programmer writes serial code
Compiler attempts to auto parallelize, vectorize
Provide guidance on how to restructure the serial code to remove semantic obstacles
Biggest challenge: tools to help write a parallel program
12/8/2018

5. 5. 3’rd party, pre compiled libraries
IA SW echo system has a strong force of gravity
Any solution, especially in native programming, must be compatible with existing, non recompiled SW
As well as with 3’rd party tools
Backward compatibility is unquestioned
12/8/2018

6. 3. Heterogeneous Targets
Target: CPU + LRB
A Solution: CELO
Multi core big core IA
Many core IA
Separate physical memories
Different ISA extensions
Different OSes
Native, C/C++
A single source code base fed into a single compiler, generates a program that utilizes both core types
TBB, Cilk++ model for parallelism
MYO – system SW layer for data synchronization across the PCIe buss
Minimal (<5 keywords) language extension to express what code executes on which core type
Heterogeneous target is programmable with existing languages and existing methodologies.
12/8/2018