First slides: Prof. Stojanovic, MIT Last slides: Prof. Dally, Stanford ECE 679 -- Lecture #2 First slides: Prof. Stojanovic, MIT Last slides: Prof. Dally, Stanford

What makes it challenging High speed link chip What makes it challenging is that we have made chips so fast that the problem in link design now is in the limited bandwidth of the wires connecting the chips. For example, signals from high-speed serializer/deserializer chips connecting two line cards over a backplane, are running into the bandwidth limits of the wires due to the skin-effect and dielectric loss. In these systems in general, 3-dB bandwidth of the wires is between 1-2GHz. So, now the challenge is in making interfaces that compensate for the losses in wires. > 2 GHz signals Now, the bandwidth limit is in wires

Backplane environment So, let us revisit the backplane environment. Chips are mounted in packages, which are soldered to line cards that plug into the backplane. The channel is the complete path from one die to the other die. In the backplane environment, the signal has to traverse a number of traces to get from source to destination. Along the long horizontal traces there is line attenuation because of the losses from skin-effect and dielectric loss. But in fact sometimes the most troubling effect have not the long traces but rather the short vertical traces that connect the components of the system. We use them in order to get from the package into the line card and from line card into the connector and the backplane. These connections have impedance mismatches that cause reflections and can significantly degrade the signal. Line attenuation Reflections from stubs (vias)

Backplane channel Loss is variable Attenuation is large Same backplane Different lengths Different stubs Top vs. Bot Attenuation is large >30dB @ 3GHz But is that bad? Required signal amplitude set by noise We could model the channel that consists of these transmission lines relatively accurately, and what we end up with is a frequency response of how the channel looks like. This is a plot of a number of channels that may be existing in one backplane and you see that there is a lot of variation among them. Due to different lengths, there is different slope in attenuation, plus there are other differences, like significant ripples in frequency response, depending on which traces/layers you use. You can see that with some traces we are down to about –30dB in about 3GHz. The question really is - is that bad or we can tolerate even higher attenuations (40dB, 60dB)? Really, what bandwidth is usable? In order to understand that, you have to understand how the signal is affected by these channels and then look at how much noise there is in the channel because that sets the minimum required signal amplitude. So let’s look at how the signal is degraded next.

Inter-symbol interference (ISI) Channel is low pass Our nice short pulse gets spread out Dispersion – short latency (skin-effect, dielectric loss) Reflections – long latency (impedance mismatches – connectors, via stubs, device parasitics, package) We have a low pass channel so our narrow pulse, shown in blue, gets significantly wider and smaller at the output of the channel, as shown in green. Just to see how much wider it gets, we put these little black dots at each of the sampling points. Now if you look at the waveform of the received pulse, you can also notice that further down at some even relatively long latencies, there are some ripples in the pulse response, caused by reflections from discontinuities. Now, notice that both the precursor and postcursor samples are very large which would make it very difficult to detect correctly the bits transmitted in a sequence.

ISI Error! In this slide, we transmit a 101 pattern, and notice that a received sample that corresponds to the zero bit, only drops to about 0.3, which is a result of interference from the previous bit, by 0.2 and the next bit, by 0.1. As a result, that zero bit is detected in error. In addition to this deterministic signal degradation, we need to look at the noise in this system in order to predict the true performance. Middle sample is corrupted by 0.2 trailing ISI (from the previous symbol), and 0.1 leading ISI (from the next symbol) resulting in 0.3 total ISI As a result middle symbol is detected in error