1. Multiprocessors and Multi-computers
Chapter 7
Multiprocessors and Multi-computers

2. Multiprocessor system interconnects
Network Characteristics: the networks can be designed with many choices. The choices are based on the topology, timing control, switching and control strategy.
Timing: synchronous and asynchronous.
Switching: packet and circuit.
Control: centralized and distributed.

4. Hierarchical bus system
Local bus: buses implemented on pcb.
Backplane bus: Backplane is a printed circuit on which many connectors are used to plug in functional boards. A system bus consisting of shared signal paths and utility lines is built on the backplane. This provides communication path among all plug-in boards.
I/O bus: i/o devices are connected to a computer system through an i/o bus such as the SCSI bus (small computer systems interface).

7. Crossbar switch and multiport memory
Network Stages :-
Blocking VS Non Blocking Networks:-
Cross Bar Networks:-
Cross Point Switch Design:-

9. Multiport Memory

10. Cache coherence problem
Data sharing
Process migration
I/O operation

13. Snoopy bus protocols Write- invalidate Write-update
Write-through caches
Write-back caches

15. Write once protocol
Combines the advantages of write-through and write-back invalidations. 4 cache states are:
1. Valid: the cache block, which is consistent with the memory copy, has been read from the shared memory and has not been modified.
2. invalid: the block is not found in the cache or is not consistent with the memory copy.
3. reserved: data has been written exactly once since being read from the memory. The cache is consistent with the memory.
4. Dirty: cache has been modified many times. The cache copy is the only one in the system.

16. Cache events and actions
Read-miss: when a processor wants to read a block that is not in cache, a read miss occur. If no dirty copy exists, then main memory has a consistent copy and supplies a copy to the cache. If a dirty copy exists in a remote cache, that cache will inhibit the main memory and sends a copy to the requesting cache. In all cases, the cache copy will enter the valid state after a read miss.

17. Write-hit: 1. if the copy is in the dirty or reserved state, the write can be carried out locally and the new state is dirty.
2. the state is valid, a write in-validate command is broadcast to all the caches invalidating their copies. The shared memory is written through and the resulting state is reserved after the first write.

18. Write-miss: when a processor fails to write in local cache, the copy must come either from the shared memory or from a remote cache with a dirty block.
Read hit: read-hit can always be performed in a local cache without causing a state transition.
Block replacement: if a copy is dirty, it has to be written back to main memory by block replacement.

20. 3 generations of multicomputers

21. Message passing schemes
Message format: a message is the logical unit for inter node communication. It is often assembled from an arbitrary number of fixed length packets, thus it may have a variable length.
A packet is the basic unit containing the destination address for routing purposes. Because different packets may arrive at the destination asynchronously, a sequence number is needed in each packet to allow reassembly of the message transmitted.

23. A packet can be further divided into fixed-length flits(flow control digits). Routing information and sequence number occupy the header flits. The remaining flits are the data elements.
In multicomputers with store-and-forward routing, packets are the smallest unit of transmission. In wormhole-routed networks, packets are further divided into flits.
The packet length is determined by the routing scheme and network implementation. Typical packet length range from 64 to 512 bits. The sequence number may occupy one to two flits depending on the message length. Other factors affecting the choice of packet and flit sizes include channel bandwidth, router design,network traffic intensity etc.

24. Store-and-forward Routing
Packets are the basic unit of information flow.
Each node is required to use a packet buffer. A packet is transmitted from a source node to a destination node through a sequence of intermediate nodes.
When a packet reaches an intermediate node, it is first stored in buffer. Then it is forwarded to the next node if the desired output channel and a packet buffer in the receiving node are available.
The latency in this is directly proportional to the distance between the source and the destination.

25. Wormhole routing
Packet is divided into smaller flits. Flit buffers are used. Transmission is done through a sequence of routers.
All flits in the same packet are transmitted in order as inseparable companions in a pipelined fashion.
Asynchronous pipeline

27. Latency analysis: a time comparison between store-and-forward and wormhole routed networks.
L= length of packet
W= channel bandwidth
D= the distance
F= flit length

30. Communication latency
Tsf= L/W (D+1)
Twh= L/W + F/W(D)
In store, Tsf is directly proportional to D.
For wormhole: if L>>F, then D has a negligible effect on the routing latency.