Asynchronous Counters 2 ©Paul Godin Last update Sept 2009

Truncating Truncating is when a counter is prevented from reaching its maximum modulus. For example, a 3-bit mod-5 counter will have 5 unique states but will not have the maximum modulus of 23, or mod-8. 000 001 010 011 100 Values 101, 110 and 111 are not included in this sequence

Truncating Method The most common method of truncating a count is to: Detect the presence of the first unwanted value using logic gates Immediately reset or preset the counter back to the desired starting state

Truncating Method 101 Immediate Reset Next natural state 000 100 001 The time from detection to an immediate reset is the time it takes for a signal to travel through the logic gates (nanoseconds). 011 010

Truncating Circuit Detect 101 Counter Reset all

Truncating circuit in EWB

In-Class EWB Exercise Create a 3-bit MOD-7 up Counter with the starting sequence of “000”. Create a 4-bit MOD-10 Up Counter with a starting sequence of “0001”. Measure the duration of the truncating pulse.

Frequency Division A typical application for asynchronous counters is frequency division. Example: Use a 60 Hz source to supply 1 pulse per second (1 pps) Mod-6 10Hz Mod-10 60Hz 1Hz

Frequency Division Mod-6 QC Mod-10 QD 1Hz 60Hz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 000 001 010 011 100 101 DCBA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 CBA 000 001 010 011 100 101 Note the MSB has a frequency of 1/6th the input frequency (at 33% Duty Cycle) Note the MSB has a frequency of 1/10th the input frequency (at 20% Duty Cycle)

In-Class Exercise There is another method for frequency division... Mod-60 60Hz QMSB 1Hz Questions: How many flip flops are required for a mod-60 counter? What is the truncating binary value?

Count Direction To reverse the count direction of an asynchronous counter, the following 3 circuit changes can be applied... Note that making two changes (reversing the direction twice) will revert back to the original direction.

Count Direction – Q/Q’ Q 1 J K Use the complimentary output Q for one direction Q’ for the other direction J K Q 1 Up Count Down Count

Count Direction – Edge, 1st Method Invert the clocking input to the next Flip-Flop Positive edge for one direction Negative edge for the other direction J K Q 1 Up Count J K Q 1 Down Count

Count Direction – Edge, 2nd Method Invert the clocking input to the next Flip-Flop Positive edge for one direction Negative edge for the other direction J K Q 1 Down Count J K Q 1 Up Count Note the LSB does not need to be reversed on the clock input An X-OR or an X-NOR may be used to invert a signal

Count Direction – Q/Q’ to next edge Use the complimentary output to the next clock input (Q to the edge input for one direction, Q’ for the other direction) J K Q 1 Down Count J K Q 1 Up Count

In-Class EWB Exercise Create a 3-bit counter where the count direction can be changed with a single switch (review the material for ideas)

Glitches Glitches are unwanted logic states. Glitches often last for nanoseconds or microseconds but may be long enough to affect logic design. Glitches are a natural part of Asynchronous Counters.

Glitches As the edge ripples its way through the counters, there is a time delay (propagation delay) between the LSB to the MSB output. This time delay may cause erratic operation of attached circuits that may detect the unwanted states. Glitches are a serious disadvantage of asynchronous counters.

Glitches 1 1 1 1 1 1 1 1 1 000 100 010 000

Glitches The time delay remains fixed because it is affected by the physical characteristics of the devices. The time delay is additive, so each additional flip-flop (bit) adds more delay to the MSB The greater the operating frequency, the greater the percentage of time the glitch occupies. The frequency may become so high that a new edge is propagating through the counter before the previous edge has reached the last flip-flop.

Strobing To avoid erratic operation, it may be necessary to read the output after the MSB has changed and after all anticipated glitches have past. Strobing is when the output state of a counter is read at a specific moment in time, after all the anticipated glitches have passed.

In-Class EWB Exercise Open an EWB file of a previously-built counter. Apply a high frequency to the input and measure the propagation delay between: QA and QB QA and the MSB

END ©Paul R. Godin prgodin°@ gmail.com