The University of Adelaide, School of Computer Science 23 November 2018 Lecture 2.3 Instructions: Memory Operations Chapter 2 — Instructions: Language of the Computer

Objectives Understand that MIPS-32 is a RISC architecture Demonstrate the data movement direction of load and store operations Perform the addition between base address and offset to form the effective address Verify the address alignment for word and half-word memory accesses Extend the content properly in the register for lb, lbu, lh, lhu instructions Convert between C and assembly statements Convert between assembly statements and binary representations Chapter 2 — Instructions: Language of the Computer — 2

Coverage Textbook Chapter 2.5 Chapter 2 — Instructions: Language of the Computer — 3

MIPS-32: a load/store computer MIPS-32 is a RISC architecture Data operations happen inside the register file (RF) Use load/store instructions to move data between RF and memory Chapter 2 — Instructions: Language of the Computer — 4

The University of Adelaide, School of Computer Science 23 November 2018 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at the least address of a word c.f. Little Endian: least-significant byte at the least address Chapter 2 — Instructions: Language of the Computer — 5 Chapter 2 — Instructions: Language of the Computer

Load and Store Load: read from memory Store: write to memory Chapter 2 — Instructions: Language of the Computer — 6

MIPS Memory Access Instructions The University of Adelaide, School of Computer Science 23 November 2018 MIPS Memory Access Instructions MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) # load a word from memory sw $t0, 8($s3) # store a word to memory The data are loaded (lw) from or stored (sw) to the memory The memory address, a 32-bit address, is formed by adding the offset value to the content of the base address register A 16-bit field means accessing is limited to memory locations within a region of ± 215 or ± 32,768 bytes (±213 or ± 8,192 words) of the address in the base register User the chest of drawers as an analogy to the register file Chapter 2 — Instructions: Language of the Computer — 7 Chapter 2 — Instructions: Language of the Computer

MIPS I-format Instructions The University of Adelaide, School of Computer Science 23 November 2018 MIPS I-format Instructions op rs rt offset 6 bits 5 bits 16 bits load/store instructions lw/sw $rt, offset($rs) rt: destination (for load) or source (for store) register number rs: the number of the register whose content is the base address offset: offset added to base address in rs Offset range: –215 to +215 – 1 Chapter 2 — Instructions: Language of the Computer — 8 Chapter 2 — Instructions: Language of the Computer

Machine Language – Load Instruction Load/Store Instruction Format (I format) 0xf f f f f f f c Chapter 2 — Instructions: Language of the Computer — 9

Memory Operand Example 1 The University of Adelaide, School of Computer Science 23 November 2018 Memory Operand Example 1 C code: g = h + A[8]; A is an array of words g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $t0, 32($s3) # load word add $s1, $s2, $t0 offset base register Chapter 2 — Instructions: Language of the Computer — 10 Chapter 2 — Instructions: Language of the Computer

Memory Operand Example 1 Chapter 2 — Instructions: Language of the Computer — 11

Memory Operand Example 2 The University of Adelaide, School of Computer Science 23 November 2018 Memory Operand Example 2 C code: A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word Chapter 2 — Instructions: Language of the Computer — 12 Chapter 2 — Instructions: Language of the Computer

Loading and Storing Bytes MIPS provides special instructions to move bytes lb $t0, 1($s3) # load byte from memory lbu $t0, 1($s3) # load unsigned byte from memory sb $t0, 6($s3) # store byte to memory 0x28 19 8 16-bit offset What 8 bits get loaded and stored? Load byte places the byte from memory in the rightmost 8 bits of the destination register lb: the byte is sign-extended to 32 bits lbu: the byte is zero-extended to 32 bits Store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory Leave the other bits in the memory word intact Chapter 2 — Instructions: Language of the Computer — 13

lb and lbu example Chapter 2 — Instructions: Language of the Computer — 14

Loading and Storing Half Words MIPS provides special instructions to move half words, i.e., 16 bits lh $t0, 2($s3) # load half word from memory lhu $t0, 4($s3) # load unsigned half word from memory sh $t0, 8($s3) # store half word to memory 0x29 19 8 16 bit offset The address of the harf word has to be even Byte_3 Byte_2 Byte_1 Byte_0 Chapter 2 — Instructions: Language of the Computer — 15