CSE221- Logic Design, Spring 2003 Logic Technology 22-Nov-18 Logic Technology Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

CSE221- Logic Design, Spring 2003 22-Nov-18 Overview Integrated Circuits Integration Levels Digital Logic Families Positive/Negative Logic Transmission Gates CMOS Circuits Transistors and switch models CMOS Networks Fully Complementary CMOS CMOS Transmission Gates 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Integrated Circuits (ICs) CSE221- Logic Design, Spring 2003 22-Nov-18 Integrated Circuits (ICs) An IC is a silicon semiconductor crystal (chip) that contains the electronic components of digital gates. Chip is mounted in a ceramic or plastic container. Connections are welded from the chip to external pins. Numbers of pins varies (depending on the chip’s functionality) 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

CSE221- Logic Design, Spring 2003 22-Nov-18 Levels of Integration Small-scale Integration (SSI) Several independent gates (>10) per package Medium-scale Integration (MSI) Between 10-100 gates per chip. Perform basic digital functions, e.g. 4-bit addition. Large-scale Integration (LSI) Between 100 and a few thousands of gates per chip. Implement digital systems, e.g. small processors and memories. Very Large-scale Integration (VLSI) Several thousands to over 100 million gates per chip, e.g. complex microprocessors. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

CSE221- Logic Design, Spring 2003 22-Nov-18 Table of Microprocessors History 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Digital Logic Families CSE221- Logic Design, Spring 2003 22-Nov-18 Digital Logic Families ICs are also classified based on their specific circuit technology, known as digital logic family. Each family has its own basic electronic components (NAND, NOR, and NOT gates), used to build complex digital circuits. Various digital logic families have been introduced and used over the years. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Digital Logic Families (in chronological order) CSE221- Logic Design, Spring 2003 22-Nov-18 Digital Logic Families (in chronological order) RTL: Resistor-Transistor Logic DTL: Diode-Transistor Logic TTL: Transistor-Transistor Logic ECL: Emitter-coupled Logic MOS: Metal-Oxide Semiconductor CMOS: Complementary MOS Low power dissipation, currently the MOST DOMINANT BiCMOS: Bipolar CMOS CMOS and TTL for additional current/speed GaAs: Gallium-Arsenide earliest, now obsolete widely used high-speed operation compact very high-speed operation 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Defining Characteristics of Digital Logic Families CSE221- Logic Design, Spring 2003 22-Nov-18 Defining Characteristics of Digital Logic Families Fan-in: Number of gate inputs. Fan-out: Number of standard loads a gate’s output can drive. Noise margin: max external noise tolerated. Power dissipation: power consumed by the gate (dissipated as heat). Propagation delay: time required for an input signal change to be observed at an output line. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

CSE221- Logic Design, Spring 2003 22-Nov-18 Propagation Delay One of the most important design parameters (if not THE most important!) The maximum propagation delay (tpd) determines the circuit’s speed. tPHL: high-to-low propagation time tPLH: low-to-high propagation time tpd = max(tPHL, tPLH) 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Propagation Delay (cont.) CSE221- Logic Design, Spring 2003 22-Nov-18 Propagation Delay (cont.) 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Positive and Negative Logic CSE221- Logic Design, Spring 2003 22-Nov-18 Positive and Negative Logic Two different assignments of signal levels to logic values: Positive logic: H  1 L  0 Negative logic: H  0 L  1 IC data sheets define digital gates in terms of signal values; user decides on positive or negative logic. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Demonstration of Positive/Negative Logic CSE221- Logic Design, Spring 2003 22-Nov-18 Demonstration of Positive/Negative Logic 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

Positive and Negative Logic (cont.) CSE221- Logic Design, Spring 2003 22-Nov-18 Positive and Negative Logic (cont.) Conversion between positive and negative logic: Interchange 0’s and 1’s at gate’s inputs and outputs. This is the same as taking the dual! Remember to include/remove the polarity indicators. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

TTL Logic Levels and Noise Margins CSE221- Logic Design, Spring 2003 22-Nov-18 TTL Logic Levels and Noise Margins Asymmetric, unlike CMOS CMOS can be made compatible with TTL “T” CMOS logic families 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

CSE221- Logic Design, Spring 2003 22-Nov-18 CMOS vs. TTL Levels TTL levels CMOS levels CMOS with TTL Levels -- HCT, FCT, VHCT, etc. 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)

TTL differences from CMOS CSE221- Logic Design, Spring 2003 22-Nov-18 TTL differences from CMOS Asymmetric input and output characteristics. Inputs source significant current in the LOW state, leakage current in the HIGH state. Output can handle much more current in the LOW state (saturated transistor). Output can source only limited current in the HIGH state (resistor plus partially-on transistor). TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS). 22-Nov-18 Chapter 2-iii: Combinational Logic Circuits (Sections 2.8 and A.2.8)