Project 1: Counter Modules

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Presentation transcript:

Project 1: Counter Modules Project 352: Stop Watch Project 1: Counter Modules (Pure Combinational) -MSINC (Mode Selectable Increment/Decrement) CLAdder_4 (Carry Lookahead Adder) M10vg (Mod 10 value generator) M6vg (Mod 6 value generator) Mux21_4 (4-bit 2 to 1 Mux)

Carry Lookahead Adder - PFA(Partial Full Adder) - CLU_2(Carry Lookahead Unit for 2-bit Adder)

Mod generator 4-bit 2-to-1 Mux Fill out the truth table for both M10vg and M6vg. Generate using CAFÉ Implement the design in design architect(da) 4-bit 2-to-1 Mux Understand how 1-bit 2-to-1 Mux works Duplicate the muxes 4 times

MSINC