UNIT 4 Control Unit

Single CPU Bus CPU Bus MUX Temp PC R0 R(n-1) Instruction Decoder IR MAR MDR Z Y ALU Carry In Address Lines Data Lines Constant Values Select ADD SUB AND OR XOR Control Signals CPU Bus A B

Instruction Execution Fetch the content of a given memory location and load them into a CPU registers. Store a word of data from a CPU register into a given memory location. Transfer a word of data from one CPU register to another or to the ALU. Perform an arithmetic or logic operation and store the result in a CPU register.

Fetching a word from memory MAR <- [R1] Read Wait form the MFC Signal R2 -> [MDR]

Storing word in Memory MAR <- [R1] MDR <- [R2], Write Wait for MFC

Register Transfer Ri are controlled by, Riin and Riout Riin =1,data is available on the common bus are loaded into Ri Riout = 1,the contents of register Ri are placed on the bus and if it is 0, the bus can be used for transferring data from other registers.

Performing arithmetic or logical operation R1out,Yin R2out,Add,Zin Zout,R3in

Execution of complete instruction ADD (R3),R1 Executing this instruction requires following actions, Fetch the instruction Fetch the first operand Perform the addition Load the result into R1 Control sequence of instruction are,R PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout, PCiin,WMFC MDRout,IRin R3out,MARin,Read R1out,Yin,WMFC MDRout,Add,Zin Zout,R1in,End

Branching Control sequence for an unconditional branch instruction PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Zout, PCiin,WMFC MDRout,Irin PCout,Yin Offset-field-of-IRout,Add,Zin Zout,PCin,End

Hardwired Control Control Signals Clock Control Step Counter Decoder/Encoder Condition Codes Status Flags Control Signals CLK

Detail Block Diagram Step Decoder Control Signals Clock Control Step Counter IR Decoder/Encoder Condition Codes Status Flags Control Signals CLK Step Decoder T1 T2 Tn Instruction Decoder INn IN1 Reset End

Generation of Control Signal Yin=T1+T5.Add+T4.Branch+…………. Zout=T2+T7.Add+T6.Branch+…………. Branch Add T4 T5 T1 Yin Branch Add T6 T7 T1 Zout

Micro-programmed Control Basic Concept: Microinstruction and Format

Micro-programmed Control

Control-Unit Micro-architecture

Functioning

Basic Tasks of Micro-programmed Control Unit

Brach Control Logic-Two Address Field

Branch Control Logic-Single Address Field

Branch Control Logic-Variable Format

Microinstruction Execution

Taxonomy of Micro-instruction Vertical / Horizontal Microinstruction Packed / Unpacked Hard/Soft micro-programming Direct / Indirect Microinstruction

Application of Micro-programming

Subject: Computer Organization Unit-IV The Control Unit (8 Hrs) Single Bus Organization Control Unit Operations: Instruction sequencing Micro operations and Register Transfer. Hardwired Control: Design methods – State table and classical method, Design Examples - Multiplier Control unit. Micro-programmed Control: Basic concepts, Microinstructions and micro-program sequencing

Topic & Contents Planned Topic & Contents Covered Teaching Plan Lect. No. Unit No. Planned Dates Topic & Contents Planned Actual Dates Topic & Contents Covered No of Student Present 1 IV The Control Unit (8 Lec.) 5/8/13 Rapid fire on IInd unit, Overview of IIIrd unit , Single Bus Organization 2 6/8/13 Single Bus Organization, Control Unit Operations: 3 7/8/13 Instruction sequencing, Micro Operations and Register Transfer. 4 10/8/13 Hardwired Control: Design methods – State table and classical method, 5 12/8/13 Design Examples - Multiplier CU. 6 13/8/13 Micro-programmed Control: Basic concepts, 7 14/8/13 Microinstructions and micro- program sequencing. 8 17/8/13 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). Instruction Register (IR) 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Executing an Instruction Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR ← [[PC]] Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC ← [PC] + 4 Carry out the actions specified by the instruction in the IR (execution phase). 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Processor Organization Datapath MDR HAS TWO INPUTS AND TWO OUTPUTS lines Data Address bus Memory Carry-in ALU PC MAR MDR Y Z Add XOR Sub IR TEMP R0 control Control signals R n 1 - ( ) Instruction decoder and Internal processor control logic A B Figure . Single-bus organization of the datapath inside a processor. MUX Select Constant 4 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Executing an Instruction Transfer a word of data from one processor register to another or to the ALU. Perform an arithmetic or a logic operation and store the result in a processor register. Fetch the contents of a given memory location and load them into a processor register. Store a word of data from a processor register into a given memory location. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Register Transfers B A Z ALU Y in out R i b us Internal processor Constant 4 MUX Select 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Register Transfers All operations and data transfers are controlled by the processor clock. Figure : Input and output gating for one register bit. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit B A Z ALU Y in out R i b us Internal processor Constant 4 MUX Select D Q Clock 1 R i out in Bus 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Performing an Arithmetic or Logic Operation The ALU is a combinational circuit that has no internal storage. ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z. What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3? R1out, Yin R2out, SelectY, Add, Zin Zout, R3in 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Fetching a Word from Memory Address into MAR; issue Read operation; data into MDR. MDR Memory-bus Figure : Connection and control signals for register MDR data lines Internal processor b us out outE in inE 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Fetching a Word from Memory The response time of each memory access varies (cache miss, memory-mapped I/O,…). To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC). Move (R1), R2 MAR ← [R1] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 ← [MDR] R1out, MARin, Read MDRinE, WMFC MDRout, R2in 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Storing a Word in Memory The desire address is loaded into MAR Then data to be written are loaded into MDR and a write command is issued. Move R2,(R1) R1out, MARin R2out MDRin, Write MDRoutE, WMFC 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Execution of a Complete Instruction Add (R3), R1 Fetch the instruction Fetch the first operand (the contents of the memory location pointed to by R3) Perform the addition Load the result into R1 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Architecture B A Z ALU Y in out R i b us Internal processor Constant 4 MUX Select 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Execution of a Complete Instruction lines Data Address bus Memory Carry-in ALU PC MAR MDR Y Z Add XOR Sub IR TEMP R0 control Control signals R n 1 - ( ) Instruction decoder and Internal processor control logic A B Single-bus organization of the datapath inside a processor. MUX Select Constant 4 Add (R3), R1 Step Action 1 PC out , MAR in Read, Select4, Add, Z 2 Y WMFC 3 MDR IR 4 R3 Read 5 R1 6 Select Y, 7 End Figure: Control sequence for execution of the instruction Add (R3),R1. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Execution of Branch Instructions A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction. The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. Conditional branch 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Execution of Branch Instructions Step Action 1 PC , MAR , Read, Select4, Add, Z out in in 2 Z , PC , Y , WMFC out in in 3 MDR , IR out in 4 Offset-field-of-IR out Add, Z in , 5 Z , PC , End out in Figure: Control sequence for an unconditional branch instruction. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Control sequence for conditional branch instruction Need to Check the status of the condition codes before loading a new value into the PC. For e.g branch-on-negative (Branch<0) instruction. The step 4 is replaced with……………….. Offset-field-of-IR out Add, Z In, If N = 0 then END Thus if N=0 the processor returns to step 1 immediately after step 4. If N=1 Step 5 is performed to load a new value into the PC, thus performing the branch operation 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. Two categories: hardwired control microprogrammed control Hardwired system can operate at high speed; but with little flexibility. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Hardwired control design • State table method – Standard algorithmic approach to sequential circuit design. • Delay element method – Based on clock delay elements for control signal timing. • Sequence-counter method – Uses counters for timing purposes. • PLA method – Programmable Logic Array 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Hardwired control design CLK Control step Clock counter External inputs Decoder/ IR encoder Condition codes Control signals 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Detailed Block Description External inputs Figure: Separation of the decoding and encoding functions. Encoder Reset CLK Clock Control signals counter Run End Condition codes decoder Instruction Step decoder Control step IR T 1 2 n INS m 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Generating Zin Zin = T1 + T6 • ADD + T4 • BR + … Branch Add T T 4 6 T 1 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Generating End End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +… Figure : Generation of the End control signal. T 7 Add Branch Branch<0 5 End N 4 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Multiplier Control Circuit 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Control Signal 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit State table method 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Delay Element Method 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Hardwired Control Unit- advantages 1. Minimizes the average number of clock cycles needed per instruction 2. occupies a relatively small area (typically 10%) of the CPU chip area 3. High efficiency in terms of operation speed 4. is to minimize cost of the circuit 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Problems With Hardwired Designs Complex sequencing & micro-operation logic Difficult to design and test Inflexible design Large design turn around time for complex design Difficult to add new instructions 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Microprogrammed Control

STES-Train the Trainer Program Unit-IV The Control Unit Overview Control signals are generated by a program similar to machine language programs. Control Word (CW); microroutine; microinstruction PC in out MAR Read MDR IR Y Select Add Z R1 R3 WMFC End 1 Micro - instruction 2 3 4 5 6 7 Figure : An example of microinstructions. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Overview Step Action 1 PC out , MAR in Read, Select4, Add, Z 2 Y WMF C 3 MDR IR 4 R3 Read 5 R1 6 SelectY, 7 End Figure: Con trol sequence for execution of the instruction Add (R3),R1. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Overview Control store Figure : Basic organization of a microprogrammed control unit. store Control generator Starting address CW Clock m P C IR One function cannot be carried out by this simple organization. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Overview The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action. Use conditional branch microinstruction. Address Microinstruction PC , MAR , Read, Select4, Add, Z out in in 1 Z , PC , Y , WMF C out in in 2 MDR , IR out in 3 Branch to starting address of appropriate microroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 If N=0, then branch to microinstruction 26 Offset-field-of-IR , SelectY, Add, Z out in 27 Z , PC , End out in Figure: Microroutine for the instruction Branch<0. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Overview External inputs Starting and Condition IR branch address codes generator Clock m P C Control CW store Figure : Organization of the control unit to allow conditional branching in the microprogram. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Microinstructions A straightforward way to structure microinstructions is to assign one bit position to each control signal. However, this is very inefficient. The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive. All mutually exclusive signals are placed in the same group in binary coding. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Partial Format for the Microinstructions F2 (3 bits) 000: No transfer 001: PC in 010: IR 011: Z 100: R0 101: R1 110: R2 111: R3 F1 F2 F3 F4 F5 F1 (4 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits) 0000: No transfer 0001: PC out 0010: MDR 0011: Z 0100: R0 0101: R1 0110: R2 0111: R3 1010: TEMP 1011: Offset 001: MAR 010: MDR 011: TEMP 100: Y 0000: Add 0001: Sub 1111: XOR 16 ALU functions 00: No action 01: Read 10: Write F6 F7 F8 F6 (1 bit) F7 (1 bit) F8 (1 bit) 0: SelectY 1: Select4 0: No action 1: WMFC 0: Continue 1: End Figure : An example of a partial format for field-encoded microinstructions. Microinstruction 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Further Improvement Enumerate the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code. Vertical organization Horizontal organization 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Microprogram Sequencing If all microprograms require only straightforward sequential execution of microinstructions except for branches, letting a μPC governs the sequencing would be efficient. However, two disadvantages: Having a separate microroutine for each machine instruction results in a large total number of microinstructions and a large control store. Longer execution time because it takes more time to carry out the required branches. Example: Add src, Rdst Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect forms). 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Microinstruction Sequencing Micro-program control unit consisting two part: the control memory that stores the microinstruction & sequencing circuit that controls the generation of the next address Techniques: Two address field Single address field Variable format 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit - Bit-ORing - Wide-Branch Addressing - WMFC 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Mode Contents of IR OP code 1 Rsrc Rdst 11 10 8 7 4 3 Address Microinstruction (octal) 000 PC out , MAR in , Read, Select 4 , Add, Z 001 Z , PC , Y , WMFC 002 MDR , IR 003 m Branch { ¬ 101 (from Instruction decoder); 5,4 [IR 10,9 ]; 3 121 Rsrc , Read, Select4, Add, Z 122 , Rsrc 123 170 , Read, WMFC 171 172 Rdst , SelectY 173 , Rdst , End 10 ] × 9 8 ]} 170; ]}, WMFC 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Microinstructions with Next-Address Field The microprogram we discussed requires several branch microinstructions, which perform no useful operation in the datapath. A powerful alternative approach is to include an address field as a part of every microinstruction to indicate the location of the next microinstruction to be fetched. Pros: separate branch microinstructions are virtually eliminated; few limitations in assigning addresses to microinstructions. Cons: additional bits for the address field (around 1/6) 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Microinstructions with Next-Address Field Figure : Microinstruction-sequencing organization. Condition codes IR Decoding circuits Control store Next address Microinstruction decoder Control signals Inputs External m A R I STES-Train the Trainer Program Unit-IV The Control Unit 11/12/2018

STES-Train the Trainer Program Unit-IV The Control Unit F1 (3 bits) 000: No transfer 001: PC out 010: MDR 011: Z 100: Rsrc 101: Rdst 110: TEMP F0 F1 F2 F3 F0 (8 bits) F2 (3 bits) F3 (3 bits) in 010: IR 001: MAR F4 F5 F6 F7 F5 (2 bits) F4 (4 bits) F6 (1 bit) 0000: Add 0001: Sub 0: SelectY 1: Select4 00: No action 01: Read Microinstruction Address of next microinstruction 011: TEMP 100: Y 1111: XOR 10: Write F8 F9 F10 F8 (1 bit) F7 (1 bit) F9 (1 bit) F10 (1 bit) 0: No action 1: WMFC 1: OR indsrc mode 0: NextAdrs 1: InstDec Figure . Format for microinstructions. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Implementation of the Microroutine 1 2 3 7 F9 F10 F8 F7 F6 F5 F4 F2 address Octal F0 F1 F3 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit decoder Microinstruction Control store Next address F1 F2 Other control signals F10 F9 F8 Decoder circuits Decoding Condition External codes inputs Rsrc Rdst IR out in m A R InstDec OR mode indsrc R15 R0 Figure Some details of the control-signal-generating circuitry. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit bit-ORing 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Difference between h/w & m/p A hardwired control unit has a processor that generates signals or instructions to be implemented in correct sequence. This was the older method of control that works through the use of distinct components, drums, a sequential circuit design, or flip chips. It is implemented using logic gates & flip flops. It is faster, less flexible & limited in complexity. A micro programmed control unit on the other hand makes use of a micro sequencer from which instruction bits are decoded to be implemented. It acts as the device supervisor that controls the rest of the subsystems including arithmetic and logic units, registers, instruction registers, off-chip input/output, and buses. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

Difference between h/w & m/p Attribute Hardwired Control Micro-Programmed Control Speed Fast Slow Cost of implementation More Cheaper Implementation approach Sequential circuit Programming Flexibility Not flexible, difficult to modify for new instruction Flexible, new machine instructions can easily be added. Decoding and sequencing logic Complex Systematic Application RISC µp CISC µp Control memory Absent Present Chip area required Less 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit References W. Stallings, “Computer Organization and Architecture: Designing for performance”, 6th Edition, Prentice Hall of India, 2003, ISBN 81 – 203 – 2962 – 7. C. Hamacher, V. Zvonko, S. Zaky, “Computer Organization”, McGraw Hill, 2002, 5th edition, ISBN 007-120411-3. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit

STES-Train the Trainer Program Unit-IV The Control Unit Thank You…. 11/12/2018 STES-Train the Trainer Program Unit-IV The Control Unit