GaN Switching Loss Simulation using LTSpice

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Presentation transcript:

GaN Switching Loss Simulation using LTSpice Application Brief GaN Switching Loss Simulation using LTSpice May 22, 2018

Overview GaN Systems provides Pspice/LTSpice simulation models for GaN Enhancement mode HEMT. In this presentation, a half bridge double pulse test circuit in LTSpice will be introduced and used as the test bench to evaluate switching performance under different electrical parameters. Switching losses were simulated and compared with Lab measurement

Half Bridge Double Pulse Test bench in LTSpice VDS ID DUT HS/LS Gate driver circuit

Half Bridge Double Pulse Test bench in LTSpice Set up the simulation parameters: .option temp=25 ; Junction temperature setting, adjust between 25 and 150C .param VBUS = 400; DC bus voltage .param ISW = 30; Switching Current .param RGON =10; Turn-on Gate Resistor .param RGOFF = 2; Turn-off Gate Resistor Switching test parameters .param VDRV_P = 6; Turn-on gate voltage .param VDRV_N = 3; Turn-off negative gate voltage .param DT = 100n; dead time .param T_ON = 2U; Turn-on period .param L_DPT = VBUS * (T_ON-2*DT) / ISW ; calculated L for switching current setting .param T_P = 2.5U; total period .param L_GATE =3N; gate inductance .param LS_EX= 10p; external source inductance .param L_DS =3N; power loop inductance Parasitic Inductances

Gate waveforms (Simulated vs Measured) Good correlation between simulated and measured waveforms. Parasitics: L_DS = 3nH, L_GATE = 3nH VSW LTSpice Simulation Measurement VGS spike on free-wheeling device induced by dv/dt (miller feedback) 6V 0V <0V -3V VGS -7V

Half Bridge Double Pulse Test bench in LTSpice Double Pulse Simulation Results (400V/30A) 400V/30A Hard switch-off VDS 30A Turn-off ID 400V/30A Hard switch-on 30A Turn-on

Half Bridge Double Pulse Test bench in LTSpice Switching Loss Calculation using LTSpice 400V/30A Turn-on 400V/30A Turn-off PSW = VDS*ID EON = 106uJ PSW = VDS*ID EOFF = 8uJ

Switching Loss Simulation vs Measurement

Simulated Switching Loss Turn-on loss increases with TJ due to the reduced trans- conductance at higher temperature Turn-off for GaN is small and less temperature dependent Switching Loss increases with RG.

Summary GaN E-HEMT switching losses were simulated by using a half bridge double pulse test circuit in LTSpice The simulation results were verified by the lab measurement. Although the real world measurement can be affected by many other factors, we have achieved reasonably good agreement between the simulation model and measurement. This LTSpice test circuit can be a convenient tool for end users to get started with simulation and be familiar with GaN switching characteristics to assist their design. This simulation test bench can also be used to easily evaluate GaN switching performance under different electrical parameters Click to download LTSpice simulation file

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