Assignment 4 – (a) Consider a symmetric MP with two processors and a cache invalidate write-back cache. Each block corresponds to two words in memory. The initial state of memory and the caches are shown in the next slide. Complete the state of each of the two caches after each of the references indicated at the bottom left of each subsequent slide. Assume that new entries coming to a cache replace the entry with a state of invalid (I) that has the lowest tag number. You need to show the entire cache state in each slide, not just the change! You need to turn in all the slides (in hardcopy).
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 I 100 00 10 B0 S 108 00 08 B1 S 108 00 08 B1 M 128 20 10 B2 M 110 00 10 B2 I 130 10 12 B3 I I 118 00 18 B3 120 10 28 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 Initial State 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 1: P0: read 128 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 2: P1: read 132 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 3: P0: write 128 20 15 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 4: P1: read 128 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 5: P0: reads 110 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 6: P1: reads 110 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22
Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 B0 B1 B1 B2 B2 B3 B3 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 Memory after cache write-back: 108 00 08 110 00 10 118 00 18 120 10 28 128 130 10 12 132 40 12 134 10 22