1. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 I B0 S B1 S B1 M B2 M B2 I B3 I I B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
Initial State

2. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 M B2 I B3 I I B3
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 1:
P0: read 128

3. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 M B2 I B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 2:
P1: read 132

4. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 M B0 S B1 S B1 I B2 M B2 I B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 3:
P0: write 128  20 15

5. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 M B2 I B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 4:
P1: read 128

6. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 M B2 I B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 5:
P0: reads 110

7. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 S B2 S B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
After reference 6:
P1: reads 110

8. Interconnect with Cache Coherency Manager
Processor 0
Processor 1
Block
State
Tag
Data
Block
State
Tag
Data B0 S B0 S B1 S B1 S B2 S B2 S B3 S B3 S
Interconnect with Cache Coherency Manager
Tag
Block Data
Memory
Memory after cache
write-back: