Subject Name: Microelectronics Circuits Subject Code: 10EC63 Prepared By: Sreepriya Kurup, Arshiya Sultana Department: ECE Date : 30/03/2015 11/7/2018
Content UNIT 4: Differential Amplifiers and Multistage Amplifiers 11/7/2018
UNIT 4 DIFFERENTIAL AMPLIFIERS AND MULTISTAGE AMPLIFIERS Syllabus: The MOS differential pair Operation with common mode input voltage Operation with differential input voltage Large Signal Operation Small signal operation of the MOS Differential Pair CMRR of MOS Differential pair The BJT Differential Pair Differential Amplifier with Active Load Multistage Amplifiers 11/7/2018
The MOS Differential Pair Figure shows the basic MOS differential pair. It consists of two matched transistors, Q1 and Q2 whose sources are joined together and biased by a constant-current source I. It is essential that MOSFET does not enter the triode region of operation. 11/7/2018
Operation with Common Mode Input Voltage The two gate terminals are joined together and connected to a voltage Vcm called the common-mode voltage. VG1 = VG2 = Vcm. Since Ql and Q2 are matched, it follows from symmetry that the current I will divide equally between the two transistors. Thus, iDl = iD2 = I/2 and the voltage at the sources vs = vCM - VGS 11/7/2018
VCMmin = -Vss + Vcs + Vt + Vov As long as Q1 and Q2 remain in the saturation region, the current I will divide equally between Q1 and Q2 and the voltages at the drains will not change. Thus the differential pair does not respond to or it rejects common-mode input signals. An important specification of a differential amplifier is its input common-mode range. This is the range of VCM over which the differential pair operates properly. The highest value of VCM is limited by the requirement that Q1 and Q2 remain in saturation . VCMmax= Vt + VDD – I/2 RD The lowest value of VCM is determined by the need to allow for a sufficient voltage across current. If a voltage Vcs is needed across the current source, then VCMmin = -Vss + Vcs + Vt + Vov 11/7/2018
Operation with Differential Input Voltage Here, a difference or differential input voltage is applied by grounding the gate of Q2 and applying a signal Vid to the gate of Q1 as shown in Figure. vid = vGS1 - vGS2 The differential pair responds to differential input signals by providing a corresponding differential output signal between the two drains. The current I can be steered from one transistor to the other by varying Vid in the range which defines the range of differential-mode operation. 11/7/2018
Large Signal Operation We shall now derive expressions for the drain currents iD1and iD2 in terms of the input differential signal Vid =VG1-VG2. The expression for iD1 is The expression for current iD2 is obtained by subtracting iD1 from I. 11/7/2018
The figure shows the normalized plots of currents In the MOS differential pair. The expression of drain currents iD1 and iD2 in terms of Vov. At Vid = 0, the two currents are equal to 1/2. Making Vid positive causes iD1to increase and iD2to decrease by equal amounts so as to keep the sum constant, iD1+ iD2= I. The current is steered entirely into Q1 when Vid reaches the value √2 Vov. For Vid negative, identical statements can be made by interchanging iD1 and iD2. In this case, Vid = -√2Vov steers the current entirely into Q2. 11/7/2018
Hence the expression for currents are approximated as follows: The transfer characteristics of the above equations nonlinear. This is due to the term involving vid2 . Therefore to obtain linear amplification from the differential pair, vid term should be made as small as possible. Hence the expression for currents are approximated as follows: The linearity can be increased by increasing the overdrive voltage Vov. This can be done by using smaller (W/L) ratios. The price paid for the increased linearity is a reduction in gm and hence a reduction in gain. 11/7/2018
Small Signal Operation Of The MOS Differential Pair Differential Gain: Fig 1 shows the MOS differential amplifier with input voltages vG1 and vG2. Fig 2 shows the small signal analysis of the MOS differential pair. 11/7/2018 Fig 1 Fig 2
From the symmetry of the circuit as well as because of the balanced manner in which Vid is applied, we observe that the signal voltage at the joint source connection must be zero, acting as a sort of virtual ground. A major advantage of diifferential pair configuration is that ,a signal ground is established at the source terminals of the transistors without resorting to the use of a large bypass capacitor. Assuming Vid/2 ≪ Vov, the condition for the small-signal approximation, the changes resulting in the drain currents of QI and Q2 will be proportional to Vgs1 and Vgs2, respectively. Thus Ql will have a drain current increment gm(Vid/2) and Q2 will have a drain current decrement gm( Vid/2), where gm denotes the transconductance of the devices. gm = 𝑰 𝑽𝒐𝒗 11/7/2018
If the output is taken single-ended ,the resulting gain becomes 𝑉𝑜1 𝑣𝑖𝑑 = - ½ gm RD or 𝑉𝑜2 𝑣𝑖𝑑 = ½ gm RD If the output is taken differentially, the gain becomes Ad = 𝑣𝑜2−𝑣01 𝑣𝑖𝑑 = gm RD Thus, another advantage of taking the output differentially is an increase in gain by a factor of 2 (6dB). 11/7/2018
Effect of MOSFET’s r0: Fig 1 shows MOS differential amplifier with ro and Rss taken into account. Fig 2 shows the equivalent circuit for determining the differential gain. Each of the two halves of the differential amplifier circuit is a common source amplifier, known as its differential "half-circuit." From the equivalent circuit , 11/7/2018 Fig 2 Fig 1
Common Mode Gain and Common Mode Rejection Ratio (CMRR) Fig 1 shows the MOS differential amplifier with a common-mode input signal Vicm. Fig 2 shows the equivalent circuit for determining the common-mode gain (with ro ignored). Each half of the circuit is known as the "common-mode half-circuit.“ When the output of the differential pair is taken single endedly: |Acm| = 𝑅𝐷 2𝑅𝑆𝑆 , |Ad| = ½ gm RD CMRR = |Ad|/|Acm| = gm Rss When the output is taken differentially, |Acm| = 𝑣02−𝑣01 𝑣𝑖𝑐𝑚 = 0, |Ad| = = 𝑣02−𝑣01 𝑣𝑖𝑑 = gm RD CMRR = |Ad|/|Acm| = ∞ 11/7/2018 Fig 1 Fig 2
THE BJT DIFFERENTIAL PAIR It is very similar to the MOSFET circuit and consists of two matched transistors, Q1 and Q2 whose emitters are joined together and biased by a constant-current source I. It is essential that the collector circuits be such that Q1 and Q2 never enter saturation. 11/7/2018
Large Signal Operation Of BJT Differential Amplifier But iE1 + iE2 = I and vB1 – vB2 = vid, we can write the expressions for emitter currents in terms of vid as iC1 and iC2 can be obtained by multiplying the emitter currents with 𝛼. The formulae for emitter current in terms of emitter voltage ve is 11/7/2018
The amplifier responds only to the difference voltage Vid The amplifier responds only to the difference voltage Vid. That is, if VB1= VB2 = VCM, the current I divides equally between the two transistors irrespective of the value of the common-mode voltage VCM. Another important observation is that a relatively small difference voltage Vid will cause the current I to flow almost entirely in one of the two transistors .. Figure shows a plot of the two collector currents (assuming 𝛼=1)as a function of the differential input signal. This is a normalized plot that can be used universally. Note that a difference voltage of about 4VT(= 100 m V) is sufficient to switch the current almost entirely to one side of the BIT pair. Note that this is much smaller than the corresponding voltage for the MOS pair, √2Vov. The fact that such a small signal can switch the current from one side of the BJT differential pair to the other means that the BJT differential pair can be used as a fast current switch. Another reason for the high speed of operation of the differential device as a switch is that neither of the transistors saturates. 11/7/2018
The linear region of operation can be extended by including resistors in the emitters. Fig 2 shows the transfer characteristics for three different values of Re. Fig 1 Fig 2 11/7/2018
Small Signal Operation of the BJT Differential Pair Figure shows the current and voltages in the differential amplifier when a small input signal vid is applied . The expression for collector currents when vid is applied is After doing some manipulations the collector currents can also be written as 11/7/2018
The incremental (or signal) current component ic is given by When Vid = 0, the bias current divides equally between the two transistors of the pair. Thus each transistor is biased at an emitter current of I/2. When a "small-signal" Vid is applied differentially (i.e., between the two bases), the collector current of Q1 increases by an increment ic and that of Q2 decreases by an equal amount. This ensures that the sum of the total currents in Q1 and Q2 remains constant, as constrained by the current-source bias. The incremental (or signal) current component ic is given by ic = 𝛼𝐼 2𝑉𝑇 𝑣𝑖𝑑 2 The transconductance of Q1 and Q2 is given by gm = 𝛼𝐼/2 𝑣𝑇 . Therefore, the collector current of Q1 will increase by gm vid/2 and the collector current of Q2 will decrease by gm vid/2. 11/7/2018
Differential voltage gain: For small difference voltages vid << 2VT , the collector currents are given by iC1 = IC + gm Vid/2 and iC2 = IC –gm vid/2 Voltages at the collector will be vC1 = (VCC – ICRC ) – gm RC vid/2 vC2= (VCC – ICRC ) + gm RC vid/2 If the output is taken differentially , then the differential gain Ad = 𝑣𝑐1−𝑣𝑐2 𝑣𝑖𝑑 =−𝑔𝑚 𝑅𝐶 If the output is taken single endedly, then the differential gain Ad = 𝑣𝑐1 𝑣𝑖𝑑 = - 1/2 gm RC 11/7/2018
Common mode gain and CMRR of BJT differential pair Figure 1 shows the differential amplifier by a common mode signal vicm. Figure 2 shows the equivalent half circuits or the common mode calculations. The resistance REE is the incremental output resistance of the bias current source. From symmetry it can be seen that the circuit is equivalent to that shown in Fig 2, where each of the two transistors Q1 and Q2 is biased at an emitter current I/2 and has a resistance 2REE in its emitter lead. 11/7/2018 Fig 1 Fig 2
The common mode output voltage vc1 will be If he output is taken differentially , then the common mode output voltage, v0 = vc1-vc2 = 0. Therefore, the common mode gain is zero and hence CMRR is infinite. If the output is taken single endedly ,the common mode gain Acm will be finite. Acm = - 𝛼 𝑅𝑐 2𝑅𝐸𝐸 , In this case Ad = ½ gm Rc, CMRR will be |Ad|/|Acm| = gm REE Similarly the common mode output voltage vc2 will be 11/7/2018
The Differential Amplifier with Active Load The Active loaded MOS differential Pair Figure 1 shows a MOS differential pair formed by transistors Q1, and Q2, loaded in a current mirror formed by transistors Q3 and Q4. Consider the case with the two input terminals connected to a dc voltage equal to the common-mode equilibrium value, in this case 0 V, as shown in Figure 2. Assuming perfect matching, the bias current I divides equally between Q1, and Q2. The drain current of Q" I/2, is fed to the input transistor of the mirror, Q3. Thus, a replica of this current is provided by the output transistor of the mirror, Q4. At the output node the two currents I/2 balance each other out, leaving a zero current to flow out to the next stage or to a load . 11/7/2018 Fig 1 Fig 2
MULTISTAGE AMPLIFIERS TWO STAGE CMOS OPAMP A reference bias current IREF is generated either externally or using on-chip circuits. The current mirror formed by Q8 and Qs supplies the differenial pair QI - Q2 with bias current. The W/L ratio of Q5 is selected to yield the desired value for the input stage bias current I . The input differential pair is actively loaded with the curent mirror formed by Q3 and Q4. The second stage consists of Q6, which is a common source amplifier actively loaded with the current source tansistor Q7 .A capacitor Cc is included in the negative-feedback path of the second stage. Its function is to enhance the stability of the opamp. 11/7/2018
The circuit consists of four stages. A Bipolar opamp The circuit consists of four stages. The input stage is differential -in, differential -out and consists of transistors Q1 and Q2, which are biased by current source Q3. The second stage is also a differential-input amplifier, but its output is taken single-endedly at the collector of Qs. This stage is formed by Q4 and Qs, which are biased by the current source Q6. Note that the conversion from differential to single-ended as performed by the second stage results in a loss of gain by a factor of 2. In addition to providing some voltage gain, the third stage, consisting of the pnp transistor Q7, provides the essential function of shifing the de level of the signal. The output stage of the op amp consists of emitter follower Q8. 11/7/2018