FINITE STATE MACHINES (FSMs) Dr. Konstantinos Tatas
ACOE161 - Digital Logic for Computers - Frederick University Finite State Machine A generic model for sequential circuits used in sequential circuit design ACOE161 - Digital Logic for Computers - Frederick University
Finite state machine block diagram State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states) Next state logic: Combinational circuit that determines the next state as a function of the current state and the input Output logic: Combinational circuit that determines the output as a function of the current state and the input ACOE161 - Digital Logic for Computers - Frederick University
Finite State Machine types Mealy machine: The output depends on the current state and input Moore machine: The output depends only on the current state State = output state machine: A Moore type FSM where the current state is the output ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University State diagram A state diagram represents the states as circles and the transitions between them as arrows annotated with inputs and outputs ACOE161 - Digital Logic for Computers - Frederick University
Analysis of FSMs with D flip-flops Determine the next state and output functions Use the functions to create a state/output table that specifies every possible next state and output for any combination of current state and input ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University EXAMPLE ACOE161 - Digital Logic for Computers - Frederick University
Next state equations and state table for example y 1 A+=Ax+Bx B+=A΄x Y=(A+B)x΄ ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University A+=Ax+Bx B+=A΄x Y=(A+B)x΄ A B x A+ B+ y 1 ACOE161 - Digital Logic for Computers - Frederick University
Sequential circuit design methodology From the description of the functionality or the state/timing diagram find the state table Encode the states if the state table contains letters Find the necessary number of flip-flops Select flip/flop type From the state table, find the excitation tables and output tables Using Karnaugh maps find the flip-flop input logic expressions Draw the circuit logic diagram ACOE161 - Digital Logic for Computers - Frederick University
Example: Design the sequential circuit of the following state diagram ACOE161 - Digital Logic for Computers - Frederick University
State/excitation table DA DB JA KA JB KB 1 ACOE161 - Digital Logic for Computers - Frederick University
Karnaugh maps for combinational circuit ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University Circuit logic diagram ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University Example: counter ACOE161 - Digital Logic for Computers - Frederick University
Self-correcting state machines The previous example did not include two possible states “011” and “111”. If the counter unexpectedly falls into one of those states there are two possibilities: The counter will recover by entering a valid state after a finite number of cycles (self-correcting) The counter will stay in a non-valid state until the f/fs are reset (not self-correcting) Finite state machines should be designed to be self correcting by assigning non-valid states to a valid next state (no don’t cares in the excitation table) ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University Example Design a self-correcting one-digit BCD counter ACOE161 - Digital Logic for Computers - Frederick University
State minimization/assignment Often the state of the circuit is not also the output and therefore the states are named abstractly State minimization and state assignment are then required State minimization is the simplification of the state diagram so that a circuit with less states produces the same output sequence State assignment is the process of assigning a binary number to each state ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University Example State values are not important just the input/output sequence States are symbolized with letters ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University State table Current state Input Next state Output a 1 b c d e f g ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University State equivalence Current state Input Next state Output a 1 b c d e f g Two states are equivalent if for any element of the input set both produce the same output and send the circuit to the same state or an equivalent one. One of the two equivalent states can be eliminated from the state diagram ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University State minimization Current state Input Next state Output a 1 b c d e f g d d e ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University State assignment Since we don’t care about the actual flip-flop values for each state we can assign each state to any binary number we like as long as each state is assigned a unique binary number If we use 3 bits to encode the states, we have possible encodings state Encoding 1 (binary) Encoding 2 (Gray) Encoding 3 a 000 b 001 010 100 c 011 d 101 e 111 ACOE161 - Digital Logic for Computers - Frederick University
ACOE161 - Digital Logic for Computers - Frederick University One-hot encoding One flip-flop per state encoding Leads to greater number of flip-flops than binary encoding but possibly to simpler logic state Encoding 1 (binary) 2 (Gray) Encoding 3 (one-hot) a 000 00001 b 001 010 00010 c 011 00100 d 101 01000 e 100 111 10000 ACOE161 - Digital Logic for Computers - Frederick University